ARM: dts: qcom: Add sdcc nodes for ipq8064
The relevant data for sdcc. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -555,5 +555,81 @@
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status = "disabled";
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perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
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};
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdcc1bam:dma@12402000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc3bam:dma@12182000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x2000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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};
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sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x2000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <192000000>;
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#mmc-ddr-1_8v;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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vqmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
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dma-names = "tx", "rx";
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};
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};
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};
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};
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