arm64: dts: imx8qxp: add adma_pwm in adma
Add PWM device and the corresponding clock gating device in adma subsystem. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -132,6 +132,19 @@ dma_subsys: bus@5a000000 {
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status = "disabled";
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};
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adma_pwm: pwm@5a190000 {
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compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
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reg = <0x5a190000 0x1000>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&adma_pwm_lpcg 1>,
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<&adma_pwm_lpcg 0>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <2>;
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power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
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};
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spi0_lpcg: clock-controller@5a400000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a400000 0x10000>;
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@ -228,6 +241,18 @@ dma_subsys: bus@5a000000 {
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power-domains = <&pd IMX_SC_R_UART_3>;
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};
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adma_pwm_lpcg: clock-controller@5a590000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a590000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "adma_pwm_lpcg_clk",
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"adma_pwm_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
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};
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i2c0: i2c@5a800000 {
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reg = <0x5a800000 0x4000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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