dt-bindings: clock: Add SC7280 VideoCC clock binding

Add device tree bindings for video clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-7-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Taniya Das 2021-07-13 20:42:22 +05:30 committed by Stephen Boyd
parent 3e0f01d6c7
commit f1f5a30385
2 changed files with 31 additions and 2 deletions

View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2 %YAML 1.2
--- ---
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml# $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
@ -11,10 +11,11 @@ maintainers:
description: | description: |
Qualcomm video clock control module which supports the clocks, resets and Qualcomm video clock control module which supports the clocks, resets and
power domains on SDM845/SC7180/SM8150/SM8250. power domains on Qualcomm SoCs.
See also: See also:
dt-bindings/clock/qcom,videocc-sc7180.h dt-bindings/clock/qcom,videocc-sc7180.h
dt-bindings/clock/qcom,videocc-sc7280.h
dt-bindings/clock/qcom,videocc-sdm845.h dt-bindings/clock/qcom,videocc-sdm845.h
dt-bindings/clock/qcom,videocc-sm8150.h dt-bindings/clock/qcom,videocc-sm8150.h
dt-bindings/clock/qcom,videocc-sm8250.h dt-bindings/clock/qcom,videocc-sm8250.h
@ -23,6 +24,7 @@ properties:
compatible: compatible:
enum: enum:
- qcom,sc7180-videocc - qcom,sc7180-videocc
- qcom,sc7280-videocc
- qcom,sdm845-videocc - qcom,sdm845-videocc
- qcom,sm8150-videocc - qcom,sm8150-videocc
- qcom,sm8250-videocc - qcom,sm8250-videocc

View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H
/* VIDEO_CC clocks */
#define VIDEO_PLL0 0
#define VIDEO_CC_IRIS_AHB_CLK 1
#define VIDEO_CC_IRIS_CLK_SRC 2
#define VIDEO_CC_MVS0_AXI_CLK 3
#define VIDEO_CC_MVS0_CORE_CLK 4
#define VIDEO_CC_MVSC_CORE_CLK 5
#define VIDEO_CC_MVSC_CTL_AXI_CLK 6
#define VIDEO_CC_SLEEP_CLK 7
#define VIDEO_CC_SLEEP_CLK_SRC 8
#define VIDEO_CC_VENUS_AHB_CLK 9
#define VIDEO_CC_XO_CLK 10
#define VIDEO_CC_XO_CLK_SRC 11
/* VIDEO_CC power domains */
#define MVS0_GDSC 0
#define MVSC_GDSC 1
#endif