Samsung DTS ARM64 changes for v5.16
1. Match Exynos5433 DTS with dtschema.
2. Add an Exynos Auto v9 SoC and SADK board. The Exynos Auto v9 is a
design for automotive for In-vehicle Infotainments (IVI) and Advanced
Driver-Assistance Systems (ADAS).
This pull request brings very basic support (pinctrl, UART and UFS
storage) with a development SADK (Samsung Automotive Development Kit)
board.
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Merge tag 'samsung-dt64-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.16
1. Match Exynos5433 DTS with dtschema.
2. Add an Exynos Auto v9 SoC and SADK board. The Exynos Auto v9 is a
design for automotive for In-vehicle Infotainments (IVI) and Advanced
Driver-Assistance Systems (ADAS).
This pull request brings very basic support (pinctrl, UART and UFS
storage) with a development SADK (Samsung Automotive Development Kit)
board.
* tag 'samsung-dt64-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: add minimal support for exynosautov9 sadk board
arm64: dts: exynos: add initial support for exynosautov9 SoC
arm64: dts: exynos: add proper comaptible FSYS syscon in Exynos5433
arm64: dts: exynos: align operating-points table name with dtschema in Exynos5433
Link: https://lore.kernel.org/r/20211013162418.43072-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f202bd97c6
@ -199,6 +199,12 @@ properties:
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||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
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- const: samsung,exynos7
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- description: Exynos Auto v9 based boards
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items:
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- enum:
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- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
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- const: samsung,exynosautov9
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required:
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- compatible
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@ -2,4 +2,5 @@
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dtb-$(CONFIG_ARCH_EXYNOS) += \
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exynos5433-tm2.dtb \
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exynos5433-tm2e.dtb \
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exynos7-espresso.dtb
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exynos7-espresso.dtb \
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exynosautov9-sadk.dtb
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@ -87,7 +87,7 @@
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status = "disabled";
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};
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bus_g2d_400_opp_table: opp-table2 {
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bus_g2d_400_opp_table: opp-table-2 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -117,7 +117,7 @@
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};
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};
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bus_g2d_266_opp_table: opp-table3 {
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bus_g2d_266_opp_table: opp-table-3 {
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compatible = "operating-points-v2";
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opp-267000000 {
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@ -137,7 +137,7 @@
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};
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};
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bus_gscl_opp_table: opp-table4 {
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bus_gscl_opp_table: opp-table-4 {
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compatible = "operating-points-v2";
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opp-333000000 {
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@ -151,7 +151,7 @@
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};
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};
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bus_hevc_opp_table: opp-table5 {
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bus_hevc_opp_table: opp-table-5 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -175,7 +175,7 @@
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};
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};
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bus_noc2_opp_table: opp-table6 {
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bus_noc2_opp_table: opp-table-6 {
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compatible = "operating-points-v2";
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opp-400000000 {
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@ -239,7 +239,7 @@
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};
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};
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cluster_a53_opp_table: opp-table0 {
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cluster_a53_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -285,7 +285,7 @@
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};
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};
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cluster_a57_opp_table: opp-table1 {
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cluster_a57_opp_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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@ -1132,7 +1132,7 @@
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};
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syscon_fsys: syscon@156f0000 {
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compatible = "syscon";
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compatible = "samsung,exynos5433-sysreg", "syscon";
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reg = <0x156f0000 0x1044>;
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};
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1189
arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
Normal file
1189
arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
56
arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
Normal file
56
arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
Normal file
@ -0,0 +1,56 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung ExynosAutov9 SADK board device tree source
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "exynosautov9.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Samsung ExynosAuto v9 SADK board";
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compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &serial_0;
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};
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chosen {
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stdout-path = &serial_0;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x77000000>,
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<0x8 0x80000000 0x1 0x7ba00000>,
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<0xa 0x00000000 0x2 0x00000000>;
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};
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ufs_0_fixed_vcc_reg: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "ufs-vcc";
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gpio = <&gpq0 1 GPIO_ACTIVE_HIGH>;
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regulator-boot-on;
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enable-active-high;
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};
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};
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&serial_0 {
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status = "okay";
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};
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&ufs_0_phy {
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status = "okay";
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};
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&ufs_0 {
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status = "okay";
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vcc-supply = <&ufs_0_fixed_vcc_reg>;
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vcc-fixed-regulator;
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};
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301
arch/arm64/boot/dts/exynos/exynosautov9.dtsi
Normal file
301
arch/arm64/boot/dts/exynos/exynosautov9.dtsi
Normal file
@ -0,0 +1,301 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's ExynosAuto v9 SoC device tree source
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynosautov9";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_aud;
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pinctrl2 = &pinctrl_fsys0;
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pinctrl3 = &pinctrl_fsys1;
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pinctrl4 = &pinctrl_fsys2;
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pinctrl5 = &pinctrl_peric0;
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pinctrl6 = &pinctrl_peric1;
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};
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arm-pmu {
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compatible = "arm,cortex-a76-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10000>;
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enable-method = "psci";
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10100>;
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enable-method = "psci";
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10200>;
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enable-method = "psci";
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10300>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
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};
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|
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fixed-rate-clocks {
|
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xtcxo: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
|
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clock-output-names = "oscclk";
|
||||
};
|
||||
|
||||
/*
|
||||
* Keep the stub clock for serial driver, until proper clock
|
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* driver is implemented.
|
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*/
|
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uart_clock: uart-clock {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
||||
clock-frequency = <133250000>;
|
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clock-output-names = "uart";
|
||||
};
|
||||
|
||||
/*
|
||||
* Keep the stub clock for ufs driver, until proper clock
|
||||
* driver is implemented.
|
||||
*/
|
||||
ufs_core_clock: ufs-core-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <166562500>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
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ranges = <0x0 0x0 0x0 0x20000000>;
|
||||
|
||||
gic: interrupt-controller@10101000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x10101000 0x1000>,
|
||||
<0x10102000 0x2000>,
|
||||
<0x10104000 0x2000>,
|
||||
<0x10106000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@10450000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x10450000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_aud: pinctrl@19c60000{
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x19c60000 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_fsys0: pinctrl@17740000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x17740000 0x1000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys1: pinctrl@17060000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x17060000 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys2: pinctrl@17c30000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x17c30000 0x1000>;
|
||||
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@10230000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x10230000 0x1000>;
|
||||
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10830000 {
|
||||
compatible = "samsung,exynosautov9-pinctrl";
|
||||
reg = <0x10830000 0x1000>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@10460000 {
|
||||
compatible = "samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x10460000 0x10000>;
|
||||
};
|
||||
|
||||
syscon_fsys2: syscon@17c20000 {
|
||||
compatible = "samsung,exynosautov9-sysreg", "syscon";
|
||||
reg = <0x17c20000 0x1000>;
|
||||
};
|
||||
|
||||
/* USI: UART */
|
||||
serial_0: uart@10300000 {
|
||||
compatible = "samsung,exynos850-uart";
|
||||
reg = <0x10300000 0x100>;
|
||||
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus_dual>;
|
||||
clocks = <&uart_clock>, <&uart_clock>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_0_phy: ufs0-phy@17e04000 {
|
||||
compatible = "samsung,exynosautov9-ufs-phy";
|
||||
reg = <0x17e04000 0xc00>;
|
||||
reg-names = "phy-pma";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&xtcxo>;
|
||||
clock-names = "ref_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_0: ufs0@17e00000 {
|
||||
compatible ="samsung,exynosautov9-ufs";
|
||||
|
||||
reg = <0x17e00000 0x100>, /* 0: HCI standard */
|
||||
<0x17e01100 0x410>, /* 1: Vendor-specific */
|
||||
<0x17e80000 0x8000>, /* 2: UNIPRO */
|
||||
<0x17dc0000 0x2200>; /* 3: UFS protector */
|
||||
reg-names = "hci", "vs_hci", "unipro", "ufsp";
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ufs_core_clock>,
|
||||
<&ufs_core_clock>;
|
||||
clock-names = "core_clk", "sclk_unipro_main";
|
||||
freq-table-hz = <0 0>, <0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
|
||||
phys = <&ufs_0_phy>;
|
||||
phy-names = "ufs-phy";
|
||||
samsung,sysreg = <&syscon_fsys2>;
|
||||
samsung,ufs-shareability-reg-offset = <0x710>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "exynosautov9-pinctrl.dtsi"
|
||||
Loading…
x
Reference in New Issue
Block a user