Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
Pull sparc updates from David Miller: 1) Recognize M8 cpus, just basic chip ID matching, from Allen Pais. 2) Prevent crashes when bringing up sunvdc virtual block devices in some environments. From Jim Quigley. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sunvdc: prevent sunvdc panic when mpgroup disk added to guest domain sparc64: Increase max_phys_bits to 51 and VA bits to 53 for M8. sparc64: recognize and support sparc M8 cpu type sparc64: properly name the cpu constants
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commit
f213ad386b
@ -47,10 +47,26 @@
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#define SUN4V_CHIP_NIAGARA5 0x05
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#define SUN4V_CHIP_SPARC_M6 0x06
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#define SUN4V_CHIP_SPARC_M7 0x07
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#define SUN4V_CHIP_SPARC_M8 0x08
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#define SUN4V_CHIP_SPARC64X 0x8a
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#define SUN4V_CHIP_SPARC_SN 0x8b
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#define SUN4V_CHIP_UNKNOWN 0xff
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/*
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* The following CPU_ID_xxx constants are used
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* to identify the CPU type in the setup phase
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* (see head_64.S)
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*/
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#define CPU_ID_NIAGARA1 ('1')
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#define CPU_ID_NIAGARA2 ('2')
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#define CPU_ID_NIAGARA3 ('3')
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#define CPU_ID_NIAGARA4 ('4')
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#define CPU_ID_NIAGARA5 ('5')
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#define CPU_ID_M6 ('6')
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#define CPU_ID_M7 ('7')
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#define CPU_ID_M8 ('8')
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#define CPU_ID_SONOMA1 ('N')
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#ifndef __ASSEMBLY__
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enum ultra_tlb_layout {
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@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
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sparc_pmu_type = "sparc-m7";
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break;
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case SUN4V_CHIP_SPARC_M8:
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sparc_cpu_type = "SPARC-M8";
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sparc_fpu_type = "SPARC-M8 integrated FPU";
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sparc_pmu_type = "sparc-m8";
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break;
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case SUN4V_CHIP_SPARC_SN:
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sparc_cpu_type = "SPARC-SN";
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sparc_fpu_type = "SPARC-SN integrated FPU";
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@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
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case SUN4V_CHIP_NIAGARA5:
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case SUN4V_CHIP_SPARC_M6:
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case SUN4V_CHIP_SPARC_M7:
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case SUN4V_CHIP_SPARC_M8:
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case SUN4V_CHIP_SPARC_SN:
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case SUN4V_CHIP_SPARC64X:
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rover_inc_table = niagara_iterate_method;
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@ -424,22 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type)
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nop
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70: ldub [%g1 + 7], %g2
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cmp %g2, '3'
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cmp %g2, CPU_ID_NIAGARA3
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA3, %g4
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cmp %g2, '4'
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cmp %g2, CPU_ID_NIAGARA4
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA4, %g4
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cmp %g2, '5'
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cmp %g2, CPU_ID_NIAGARA5
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA5, %g4
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cmp %g2, '6'
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cmp %g2, CPU_ID_M6
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_M6, %g4
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cmp %g2, '7'
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cmp %g2, CPU_ID_M7
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_M7, %g4
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cmp %g2, 'N'
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cmp %g2, CPU_ID_M8
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_M8, %g4
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cmp %g2, CPU_ID_SONOMA1
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_SN, %g4
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ba,pt %xcc, 49f
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@ -448,10 +451,10 @@ EXPORT_SYMBOL(sun4v_chip_type)
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91: sethi %hi(prom_cpu_compatible), %g1
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or %g1, %lo(prom_cpu_compatible), %g1
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ldub [%g1 + 17], %g2
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cmp %g2, '1'
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cmp %g2, CPU_ID_NIAGARA1
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA1, %g4
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cmp %g2, '2'
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cmp %g2, CPU_ID_NIAGARA2
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA2, %g4
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@ -600,6 +603,9 @@ niagara_tlb_fixup:
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_SPARC_M7
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_SPARC_M8
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_SPARC_SN
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@ -288,10 +288,17 @@ static void __init sun4v_patch(void)
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sun4v_patch_2insn_range(&__sun4v_2insn_patch,
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&__sun4v_2insn_patch_end);
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if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN)
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_SPARC_M7:
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case SUN4V_CHIP_SPARC_M8:
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case SUN4V_CHIP_SPARC_SN:
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sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
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&__sun_m7_2insn_patch_end);
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break;
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default:
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break;
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}
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sun4v_hvapi_init();
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}
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@ -529,6 +536,7 @@ static void __init init_sparc64_elf_hwcap(void)
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sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
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sun4v_chip_type == SUN4V_CHIP_SPARC64X)
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cap |= HWCAP_SPARC_BLKINIT;
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@ -538,6 +546,7 @@ static void __init init_sparc64_elf_hwcap(void)
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sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
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sun4v_chip_type == SUN4V_CHIP_SPARC64X)
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cap |= HWCAP_SPARC_N2;
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@ -568,6 +577,7 @@ static void __init init_sparc64_elf_hwcap(void)
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sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
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sun4v_chip_type == SUN4V_CHIP_SPARC64X)
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cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
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@ -578,6 +588,7 @@ static void __init init_sparc64_elf_hwcap(void)
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sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
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sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
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sun4v_chip_type == SUN4V_CHIP_SPARC64X)
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cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
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@ -1944,12 +1944,22 @@ static void __init setup_page_offset(void)
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break;
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case SUN4V_CHIP_SPARC_M7:
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case SUN4V_CHIP_SPARC_SN:
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default:
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/* M7 and later support 52-bit virtual addresses. */
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sparc64_va_hole_top = 0xfff8000000000000UL;
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sparc64_va_hole_bottom = 0x0008000000000000UL;
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max_phys_bits = 49;
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break;
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case SUN4V_CHIP_SPARC_M8:
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default:
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/* M8 and later support 54-bit virtual addresses.
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* However, restricting M8 and above VA bits to 53
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* as 4-level page table cannot support more than
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* 53 VA bits.
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*/
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sparc64_va_hole_top = 0xfff0000000000000UL;
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sparc64_va_hole_bottom = 0x0010000000000000UL;
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max_phys_bits = 51;
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break;
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}
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}
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@ -2161,6 +2171,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
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*/
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_SPARC_M7:
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case SUN4V_CHIP_SPARC_M8:
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case SUN4V_CHIP_SPARC_SN:
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pagecv_flag = 0x00;
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break;
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@ -2313,6 +2324,7 @@ void __init paging_init(void)
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*/
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_SPARC_M7:
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case SUN4V_CHIP_SPARC_M8:
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case SUN4V_CHIP_SPARC_SN:
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page_cache4v_flag = _PAGE_CP_4V;
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break;
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@ -875,6 +875,56 @@ static void print_version(void)
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printk(KERN_INFO "%s", version);
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}
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struct vdc_check_port_data {
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int dev_no;
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char *type;
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};
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static int vdc_device_probed(struct device *dev, void *arg)
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{
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struct vio_dev *vdev = to_vio_dev(dev);
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struct vdc_check_port_data *port_data;
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port_data = (struct vdc_check_port_data *)arg;
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if ((vdev->dev_no == port_data->dev_no) &&
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(!(strcmp((char *)&vdev->type, port_data->type))) &&
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dev_get_drvdata(dev)) {
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/* This device has already been configured
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* by vdc_port_probe()
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*/
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return 1;
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} else {
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return 0;
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}
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}
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/* Determine whether the VIO device is part of an mpgroup
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* by locating all the virtual-device-port nodes associated
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* with the parent virtual-device node for the VIO device
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* and checking whether any of these nodes are vdc-ports
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* which have already been configured.
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*
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* Returns true if this device is part of an mpgroup and has
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* already been probed.
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*/
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static bool vdc_port_mpgroup_check(struct vio_dev *vdev)
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{
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struct vdc_check_port_data port_data;
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struct device *dev;
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port_data.dev_no = vdev->dev_no;
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port_data.type = (char *)&vdev->type;
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dev = device_find_child(vdev->dev.parent, &port_data,
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vdc_device_probed);
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if (dev)
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return true;
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return false;
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}
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static int vdc_port_probe(struct vio_dev *vdev, const struct vio_device_id *id)
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{
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struct mdesc_handle *hp;
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@ -893,6 +943,14 @@ static int vdc_port_probe(struct vio_dev *vdev, const struct vio_device_id *id)
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goto err_out_release_mdesc;
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}
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/* Check if this device is part of an mpgroup */
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if (vdc_port_mpgroup_check(vdev)) {
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printk(KERN_WARNING
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"VIO: Ignoring extra vdisk port %s",
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dev_name(&vdev->dev));
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goto err_out_release_mdesc;
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}
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port = kzalloc(sizeof(*port), GFP_KERNEL);
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err = -ENOMEM;
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if (!port) {
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@ -943,6 +1001,9 @@ static int vdc_port_probe(struct vio_dev *vdev, const struct vio_device_id *id)
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if (err)
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goto err_out_free_tx_ring;
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/* Note that the device driver_data is used to determine
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* whether the port has been probed.
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*/
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dev_set_drvdata(&vdev->dev, port);
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mdesc_release(hp);
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