From f24d423a5c4fbcd9789ad54454f7c805798a597a Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 7 Apr 2023 15:41:02 +0900 Subject: [PATCH] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for multi-chip device support Rework quad method for multi-chip devices by updating CFR1V in all dice in the device. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/1b5606dbcc11b3432c306a75880f05c68e927fb9.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 94 ++++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 5e021e20497b..91bc0aace516 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -139,6 +139,51 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) return 0; } +static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr) +{ + struct spi_mem_op op; + u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; + u8 cfr1v_written; + int ret; + + op = (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, + nor->bouncebuf); + + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) + return 0; + + /* Update the Quad Enable bit. */ + nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; + op = (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, + nor->bouncebuf); + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + cfr1v_written = nor->bouncebuf[0]; + + /* Read back and check it. */ + op = (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, + nor->bouncebuf); + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + if (nor->bouncebuf[0] != cfr1v_written) { + dev_err(nor->dev, "CFR1: Read back test failed\n"); + return -EIO; + } + + return 0; +} + /** * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile * register. @@ -155,47 +200,20 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) */ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) { - struct spi_mem_op op; - u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; - u8 cfr1v_written; + struct spi_nor_flash_parameter *params = nor->params; + u64 addr; + u8 i; int ret; - op = (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR1V, 0, - nor->bouncebuf); + if (!params->n_dice) + return cypress_nor_quad_enable_volatile_reg(nor, + SPINOR_REG_CYPRESS_CFR1V); - ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) - return 0; - - /* Update the Quad Enable bit. */ - nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; - op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR1V, 1, - nor->bouncebuf); - ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - cfr1v_written = nor->bouncebuf[0]; - - /* Read back and check it. */ - op = (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR1V, 0, - nor->bouncebuf); - ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] != cfr1v_written) { - dev_err(nor->dev, "CFR1: Read back test failed\n"); - return -EIO; + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; + ret = cypress_nor_quad_enable_volatile_reg(nor, addr); + if (ret) + return ret; } return 0;