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arm64: dts: renesas: Handle ADG bit for sound clk_i

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Renesas Sound has been using CPG_AUDIO_CLK_I on CPG_CORE for clock,
but this was wrong.  Instead, it needs to use CPG_MOD, so clk_i can
handle the "ADG" bit in SMSTPCR9.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> [r8a77965]
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> [r8a77965]
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87y1i3sjoc.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87wmxnsjo7.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87v8d7sjo2.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87ttsrsjnx.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87sf8bsjns.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87r0nvsjnn.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87pm3fsjni.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87o7izsjnd.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87msyjsjn9.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87lee3sjn4.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87jztnsjmy.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87il97sjmu.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87h6orsjmp.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87fs4bsjml.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87edjvsjmg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto 2023-08-22 05:57:55 +00:00 committed by Geert Uytterhoeven
parent 0bb80ecc33
commit f2802c62cc
14 changed files with 14 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -651,7 +651,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&versaclock6_bb 4>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
<&cpg CPG_MOD 922>;
status = "okay";

2
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View File

@ -112,7 +112,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
<&cpg CPG_MOD 922>;
rsnd_port: port {
rsnd_endpoint: endpoint {

4
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -10,8 +10,6 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
@ -1713,7 +1711,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -10,8 +10,6 @@
#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
#include <dt-bindings/power/r8a774b1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
/ {
compatible = "renesas,r8a774b1";
#address-cells = <2>;
@ -1597,7 +1595,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A774B1_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

2
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -1350,7 +1350,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A774C0_CLK_ZA2>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -10,8 +10,6 @@
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
#include <dt-bindings/power/r8a774e1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
/ {
compatible = "renesas,r8a774e1";
#address-cells = <2>;
@ -1809,7 +1807,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A774E1_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -9,8 +9,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
#define SOC_HAS_HDMI1
#define SOC_HAS_SATA
#define SOC_HAS_USB2_CH2
@ -2032,7 +2030,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -9,8 +9,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
@ -1903,7 +1901,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7796_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -9,8 +9,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77961-sysc.h>
#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4
/ {
compatible = "renesas,r8a77961";
#address-cells = <2>;
@ -1783,7 +1781,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A77961_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

4
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -12,8 +12,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77965-sysc.h>
#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
#define SOC_HAS_SATA
/ {
@ -1766,7 +1764,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A77965_CLK_S0D4>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

2
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -1501,7 +1501,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",

2
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -1063,7 +1063,7 @@
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
<&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.4", "ssi.3",
"src.6", "src.5",

2
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -822,7 +822,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
<&cpg CPG_MOD 922>;
ports {
#address-cells = <1>;

2
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -383,7 +383,7 @@
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
<&cpg CPG_MOD 922>;
};
&rpc {