drm/radeon: separate ring and IB handling
Both on their own are complex enough. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
3157c58972
commit
f28be81011
@ -80,7 +80,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
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rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
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trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
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ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o
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ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o
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# add async DMA block
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radeon-y += \
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319
drivers/gpu/drm/radeon/radeon_ib.c
Normal file
319
drivers/gpu/drm/radeon/radeon_ib.c
Normal file
@ -0,0 +1,319 @@
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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/*
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* IB
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* IBs (Indirect Buffers) and areas of GPU accessible memory where
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* commands are stored. You can put a pointer to the IB in the
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* command ring and the hw will fetch the commands from the IB
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* and execute them. Generally userspace acceleration drivers
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* produce command buffers which are send to the kernel and
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* put in IBs for execution by the requested ring.
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*/
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static int radeon_debugfs_sa_init(struct radeon_device *rdev);
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/**
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* radeon_ib_get - request an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the IB is associated with
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* @ib: IB object returned
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* @size: requested IB size
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*
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* Request an IB (all asics). IBs are allocated using the
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* suballocator.
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib *ib, struct radeon_vm *vm,
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unsigned size)
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{
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int r;
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r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
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if (r) {
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dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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}
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r = radeon_semaphore_create(rdev, &ib->semaphore);
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if (r) {
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return r;
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}
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ib->ring = ring;
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ib->fence = NULL;
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ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
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ib->vm = vm;
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if (vm) {
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/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
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* space and soffset is the offset inside the pool bo
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*/
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ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
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} else {
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ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
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}
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ib->is_const_ib = false;
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return 0;
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}
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/**
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* radeon_ib_free - free an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to free
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*
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* Free an IB (all asics).
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*/
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
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radeon_fence_unref(&ib->fence);
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}
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/**
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* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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* @const_ib: Const IB to schedule (SI only)
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*
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* Schedule an IB on the associated ring (all asics).
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* Returns 0 on success, error on failure.
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*
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* On SI, there are two parallel engines fed from the primary ring,
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* the CE (Constant Engine) and the DE (Drawing Engine). Since
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* resource descriptors have moved to memory, the CE allows you to
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* prime the caches while the DE is updating register state so that
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* the resource descriptors will be already in cache when the draw is
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* processed. To accomplish this, the userspace driver submits two
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* IBs, one for the CE and one for the DE. If there is a CE IB (called
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* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
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* to SI there was just a DE IB.
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*/
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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int r = 0;
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if (!ib->length_dw || !ring->ready) {
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/* TODO: Nothings in the ib we should report. */
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dev_err(rdev->dev, "couldn't schedule ib\n");
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
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if (r) {
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dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
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return r;
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}
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/* grab a vm id if necessary */
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if (ib->vm) {
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struct radeon_fence *vm_id_fence;
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vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
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radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);
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}
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/* sync with other rings */
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r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
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if (r) {
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dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (ib->vm)
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radeon_vm_flush(rdev, ib->vm, ib->ring);
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if (const_ib) {
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radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
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radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
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}
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radeon_ring_ib_execute(rdev, ib->ring, ib);
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r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
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if (r) {
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dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (const_ib) {
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const_ib->fence = radeon_fence_ref(ib->fence);
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}
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if (ib->vm)
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radeon_vm_fence(rdev, ib->vm, ib->fence);
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radeon_ring_unlock_commit(rdev, ring);
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return 0;
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}
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/**
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* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Initialize the suballocator to manage a pool of memory
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* for use as IBs (all asics).
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_pool_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->ib_pool_ready) {
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return 0;
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}
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if (rdev->family >= CHIP_BONAIRE) {
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r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_GTT_WC);
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} else {
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/* Before CIK, it's better to stick to cacheable GTT due
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* to the command stream checking
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*/
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r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT, 0);
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}
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if (r) {
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return r;
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}
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r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
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if (r) {
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return r;
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}
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rdev->ib_pool_ready = true;
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if (radeon_debugfs_sa_init(rdev)) {
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dev_err(rdev->dev, "failed to register debugfs file for SA\n");
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}
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return 0;
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}
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/**
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* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Tear down the suballocator managing the pool of memory
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* for use as IBs (all asics).
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*/
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void radeon_ib_pool_fini(struct radeon_device *rdev)
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{
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if (rdev->ib_pool_ready) {
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radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
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radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
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rdev->ib_pool_ready = false;
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}
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}
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/**
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* radeon_ib_ring_tests - test IBs on the rings
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*
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* @rdev: radeon_device pointer
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*
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* Test an IB (Indirect Buffer) on each ring.
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* If the test fails, disable the ring.
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* Returns 0 on success, error if the primary GFX ring
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* IB test fails.
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*/
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int radeon_ib_ring_tests(struct radeon_device *rdev)
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{
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unsigned i;
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int r;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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struct radeon_ring *ring = &rdev->ring[i];
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if (!ring->ready)
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continue;
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r = radeon_ib_test(rdev, i, ring);
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if (r) {
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ring->ready = false;
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rdev->needs_reset = false;
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if (i == RADEON_RING_TYPE_GFX_INDEX) {
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/* oh, oh, that's really bad */
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DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
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rdev->accel_working = false;
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return r;
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} else {
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/* still not good, but we can live with it */
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DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
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}
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}
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}
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return 0;
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
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return 0;
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}
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static struct drm_info_list radeon_debugfs_sa_list[] = {
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{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
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};
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#endif
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static int radeon_debugfs_sa_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
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#else
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return 0;
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#endif
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}
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@ -26,270 +26,8 @@
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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/*
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* IB
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* IBs (Indirect Buffers) and areas of GPU accessible memory where
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* commands are stored. You can put a pointer to the IB in the
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* command ring and the hw will fetch the commands from the IB
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* and execute them. Generally userspace acceleration drivers
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* produce command buffers which are send to the kernel and
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* put in IBs for execution by the requested ring.
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*/
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static int radeon_debugfs_sa_init(struct radeon_device *rdev);
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/**
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* radeon_ib_get - request an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the IB is associated with
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* @ib: IB object returned
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* @size: requested IB size
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*
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* Request an IB (all asics). IBs are allocated using the
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* suballocator.
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib *ib, struct radeon_vm *vm,
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unsigned size)
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{
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int r;
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r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
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if (r) {
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dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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}
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r = radeon_semaphore_create(rdev, &ib->semaphore);
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if (r) {
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return r;
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}
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ib->ring = ring;
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ib->fence = NULL;
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ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
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ib->vm = vm;
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if (vm) {
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/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
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* space and soffset is the offset inside the pool bo
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*/
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ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
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} else {
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ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
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}
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ib->is_const_ib = false;
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return 0;
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}
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/**
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* radeon_ib_free - free an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to free
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*
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* Free an IB (all asics).
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*/
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
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radeon_fence_unref(&ib->fence);
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}
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/**
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* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
|
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* @const_ib: Const IB to schedule (SI only)
|
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*
|
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* Schedule an IB on the associated ring (all asics).
|
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* Returns 0 on success, error on failure.
|
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*
|
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* On SI, there are two parallel engines fed from the primary ring,
|
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* the CE (Constant Engine) and the DE (Drawing Engine). Since
|
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* resource descriptors have moved to memory, the CE allows you to
|
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* prime the caches while the DE is updating register state so that
|
||||
* the resource descriptors will be already in cache when the draw is
|
||||
* processed. To accomplish this, the userspace driver submits two
|
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* IBs, one for the CE and one for the DE. If there is a CE IB (called
|
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* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
|
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* to SI there was just a DE IB.
|
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*/
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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int r = 0;
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if (!ib->length_dw || !ring->ready) {
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/* TODO: Nothings in the ib we should report. */
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dev_err(rdev->dev, "couldn't schedule ib\n");
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
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if (r) {
|
||||
dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* grab a vm id if necessary */
|
||||
if (ib->vm) {
|
||||
struct radeon_fence *vm_id_fence;
|
||||
vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
|
||||
radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);
|
||||
}
|
||||
|
||||
/* sync with other rings */
|
||||
r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
return r;
|
||||
}
|
||||
|
||||
if (ib->vm)
|
||||
radeon_vm_flush(rdev, ib->vm, ib->ring);
|
||||
|
||||
if (const_ib) {
|
||||
radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
|
||||
radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
|
||||
}
|
||||
radeon_ring_ib_execute(rdev, ib->ring, ib);
|
||||
r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
return r;
|
||||
}
|
||||
if (const_ib) {
|
||||
const_ib->fence = radeon_fence_ref(ib->fence);
|
||||
}
|
||||
|
||||
if (ib->vm)
|
||||
radeon_vm_fence(rdev, ib->vm, ib->fence);
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Initialize the suballocator to manage a pool of memory
|
||||
* for use as IBs (all asics).
|
||||
* Returns 0 on success, error on failure.
|
||||
*/
|
||||
int radeon_ib_pool_init(struct radeon_device *rdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (rdev->ib_pool_ready) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (rdev->family >= CHIP_BONAIRE) {
|
||||
r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
|
||||
RADEON_IB_POOL_SIZE*64*1024,
|
||||
RADEON_GPU_PAGE_SIZE,
|
||||
RADEON_GEM_DOMAIN_GTT,
|
||||
RADEON_GEM_GTT_WC);
|
||||
} else {
|
||||
/* Before CIK, it's better to stick to cacheable GTT due
|
||||
* to the command stream checking
|
||||
*/
|
||||
r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
|
||||
RADEON_IB_POOL_SIZE*64*1024,
|
||||
RADEON_GPU_PAGE_SIZE,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
|
||||
rdev->ib_pool_ready = true;
|
||||
if (radeon_debugfs_sa_init(rdev)) {
|
||||
dev_err(rdev->dev, "failed to register debugfs file for SA\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Tear down the suballocator managing the pool of memory
|
||||
* for use as IBs (all asics).
|
||||
*/
|
||||
void radeon_ib_pool_fini(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->ib_pool_ready) {
|
||||
radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
|
||||
radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
|
||||
rdev->ib_pool_ready = false;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_ib_ring_tests - test IBs on the rings
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Test an IB (Indirect Buffer) on each ring.
|
||||
* If the test fails, disable the ring.
|
||||
* Returns 0 on success, error if the primary GFX ring
|
||||
* IB test fails.
|
||||
*/
|
||||
int radeon_ib_ring_tests(struct radeon_device *rdev)
|
||||
{
|
||||
unsigned i;
|
||||
int r;
|
||||
|
||||
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
||||
struct radeon_ring *ring = &rdev->ring[i];
|
||||
|
||||
if (!ring->ready)
|
||||
continue;
|
||||
|
||||
r = radeon_ib_test(rdev, i, ring);
|
||||
if (r) {
|
||||
ring->ready = false;
|
||||
rdev->needs_reset = false;
|
||||
|
||||
if (i == RADEON_RING_TYPE_GFX_INDEX) {
|
||||
/* oh, oh, that's really bad */
|
||||
DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
|
||||
rdev->accel_working = false;
|
||||
return r;
|
||||
|
||||
} else {
|
||||
/* still not good, but we can live with it */
|
||||
DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Rings
|
||||
@ -805,22 +543,6 @@ static struct drm_info_list radeon_debugfs_ring_info_list[] = {
|
||||
{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
|
||||
};
|
||||
|
||||
static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
|
||||
{
|
||||
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
||||
struct drm_device *dev = node->minor->dev;
|
||||
struct radeon_device *rdev = dev->dev_private;
|
||||
|
||||
radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static struct drm_info_list radeon_debugfs_sa_list[] = {
|
||||
{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
@ -842,12 +564,3 @@ static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ri
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int radeon_debugfs_sa_init(struct radeon_device *rdev)
|
||||
{
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user