habanalabs: add CPU-CP packet for engine core ASID cfg
In some cases the driver cannot configure ASID of some engines due to the security level of the relevant registers. For this a new CPU-CP packet is introduced, which will allow the driver to ask the F/W to do this configuration instead. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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drivers/misc/habanalabs
@ -1059,6 +1059,26 @@ out:
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return rc;
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}
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int hl_fw_cpucp_engine_core_asid_set(struct hl_device *hdev, u32 asid)
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{
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struct cpucp_packet pkt;
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int rc;
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memset(&pkt, 0, sizeof(pkt));
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pkt.ctl = cpu_to_le32(CPUCP_PACKET_ENGINE_CORE_ASID_SET << CPUCP_PKT_CTL_OPCODE_SHIFT);
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pkt.value = cpu_to_le64(asid);
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rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
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HL_CPUCP_INFO_TIMEOUT_USEC, NULL);
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if (rc)
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dev_err(hdev->dev,
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"Failed on ASID configuration request for engine core, error %d\n",
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rc);
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return rc;
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}
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void hl_fw_ask_hard_reset_without_linux(struct hl_device *hdev)
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{
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struct static_fw_load_mgr *static_loader =
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@ -3065,6 +3065,7 @@ int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
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int hl_fw_dram_replaced_row_get(struct hl_device *hdev,
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struct cpucp_hbm_row_info *info);
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int hl_fw_dram_pending_row_get(struct hl_device *hdev, u32 *pend_rows_num);
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int hl_fw_cpucp_engine_core_asid_set(struct hl_device *hdev, u32 asid);
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int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
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bool is_wc[3]);
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int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data);
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@ -386,6 +386,9 @@ enum pq_init_status {
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*
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* CPUCP_PACKET_POWER_SET -
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* Resets power history of device to 0
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*
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* CPUCP_PACKET_ENGINE_CORE_ASID_SET -
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* Packet to perform engine core ASID configuration
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*/
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enum cpucp_packet_id {
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@ -434,6 +437,8 @@ enum cpucp_packet_id {
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CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */
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CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */
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CPUCP_PACKET_POWER_SET, /* internal */
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CPUCP_PACKET_RESERVED, /* not used */
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CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */
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};
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#define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5
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