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agp/intel: Reinforce the barrier after GTT updates

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After changing the timing between GTT updates and execution on the GPU,
we started seeing sporadic failures on Ironlake. These were narrowed
down to being an insufficiently strong enough barrier/delay after
updating the GTT and scheduling execution on the GPU. By forcing the
uncached read, and adding the missing barrier for the singular
insert_page (relocation paths), the sporadic failures go away.

Fixes: 983d308cb8 ("agp/intel: Serialise after GTT updates")
Fixes: 3497971a71 ("agp/intel: Flush chipset writes after updating a single PTE")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Andi Shyti <andi.shyti@intel.com>
Cc: stable@vger.kernel.org # v4.0+
Link: https://patchwork.freedesktop.org/patch/msgid/20200410083535.25464-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2020-04-10 09:35:35 +01:00
parent c1b5ea926d
commit f30d3ced9f
1 changed files with 3 additions and 1 deletions
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4
drivers/char/agp/intel-gtt.c
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@ -846,6 +846,7 @@ void intel_gtt_insert_page(dma_addr_t addr,
unsigned int flags) unsigned int flags)
{ {
intel_private.driver->write_entry(addr, pg, flags); intel_private.driver->write_entry(addr, pg, flags);
readl(intel_private.gtt + pg);
if (intel_private.driver->chipset_flush) if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush(); intel_private.driver->chipset_flush();
} }
@ -871,7 +872,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
j++; j++;
} }
} }
wmb(); readl(intel_private.gtt + j - 1);
if (intel_private.driver->chipset_flush) if (intel_private.driver->chipset_flush)
intel_private.driver->chipset_flush(); intel_private.driver->chipset_flush();
} }
@ -1105,6 +1106,7 @@ static void i9xx_cleanup(void)
static void i9xx_chipset_flush(void) static void i9xx_chipset_flush(void)
{ {
wmb();
if (intel_private.i9xx_flush_page) if (intel_private.i9xx_flush_page)
writel(1, intel_private.i9xx_flush_page); writel(1, intel_private.i9xx_flush_page);
} }