drm/i915/xelpg: Add multicast steering
MTL's graphics IP (Xe_LPG) once again changes the multicast register types and steering details. Key changes from past platforms: * The number of instances of some MCR types (NODE, OAAL2, and GAM) vary according to the MTL subplatform and cannot be read from fuse registers. However steering to instance #0 will always provided a non-terminated value, so we can lump these all into a single "instance0" table. * The MCR steering register (and its bitfields) has changed. Unlike past platforms, we will be explicitly steering all types of MCR accesses, including those for "SLICE" and "DSS" ranges; we no longer rely on implicit steering. On previous platforms, various hardware/firmware agents that needed to access registers typically had their own steering control registers, allowing them to perform multicast steering without clobbering the CPU/kernel steering. Starting with MTL, more of these agents now share a single steering register (0xFD4) and it is no longer safe for us to assume that the value will remain unchanged from how we initialized it during startup. There is also a slight chance of race conditions between the driver and a hardware/firmware agent, so the hardware provides a semaphore register that can be used to coordinate access to the steering register. Support for the semaphore register will be introduced in a future patch. v2: - Use Xe_LPG terminology instead of "MTL 3D" since it's the IP version we're matching on now rather than the platform. - Don't combine l3bank and mslice masks into a union. It's not related to the other changes here and we might still need both of them on some future platform. - Separate debug dumping of steering settings to a separate helper function. (Tvrtko) - Update debug dumping to include DSS ranges (and future-proof it so that any new ranges added on future platforms will also be dumped). - Restore MULTICAST bit at the end of rw_with_mcr_steering_fw() if we cleared it. Also force the MULTICAST bit to true at the beginning of multicast writes just to be safe. (Bala) Bspec: 67788, 67112 Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-14-matthew.d.roper@intel.com
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@ -41,6 +41,7 @@ static const char * const intel_steering_types[] = {
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"MSLICE",
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"LNCF",
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"GAM",
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"DSS",
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"INSTANCE 0",
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};
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@ -99,9 +100,40 @@ static const struct intel_mmio_range pvc_instance0_steering_table[] = {
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{},
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};
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static const struct intel_mmio_range xelpg_instance0_steering_table[] = {
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{ 0x000B00, 0x000BFF }, /* SQIDI */
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{ 0x001000, 0x001FFF }, /* SQIDI */
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{ 0x004000, 0x0048FF }, /* GAM */
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{ 0x008700, 0x0087FF }, /* SQIDI */
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{ 0x00B000, 0x00B0FF }, /* NODE */
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{ 0x00C800, 0x00CFFF }, /* GAM */
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{ 0x00D880, 0x00D8FF }, /* NODE */
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{ 0x00DD00, 0x00DDFF }, /* OAAL2 */
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{},
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};
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static const struct intel_mmio_range xelpg_l3bank_steering_table[] = {
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{ 0x00B100, 0x00B3FF },
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{},
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};
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/* DSS steering is used for SLICE ranges as well */
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static const struct intel_mmio_range xelpg_dss_steering_table[] = {
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{ 0x005200, 0x0052FF }, /* SLICE */
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{ 0x005500, 0x007FFF }, /* SLICE */
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{ 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
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{ 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
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{ 0x009680, 0x0096FF }, /* DSS */
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{ 0x00D800, 0x00D87F }, /* SLICE */
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{ 0x00DC00, 0x00DCFF }, /* SLICE */
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{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
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};
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void intel_gt_mcr_init(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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unsigned long fuse;
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int i;
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/*
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* An mslice is unavailable only if both the meml3 for the slice is
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@ -119,7 +151,22 @@ void intel_gt_mcr_init(struct intel_gt *gt)
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drm_warn(&i915->drm, "mslice mask all zero!\n");
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}
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if (IS_PONTEVECCHIO(i915)) {
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
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gt->type == GT_PRIMARY) {
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fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
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intel_uncore_read(gt->uncore, XEHP_FUSE4));
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/*
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* Despite the register field being named "exclude mask" the
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* bits actually represent enabled banks (two banks per bit).
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*/
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for_each_set_bit(i, &fuse, 3)
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gt->info.l3bank_mask |= 0x3 << 2 * i;
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gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;
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gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
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gt->steering_table[DSS] = xelpg_dss_steering_table;
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} else if (IS_PONTEVECCHIO(i915)) {
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gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
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} else if (IS_DG2(i915)) {
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gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
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@ -184,7 +231,19 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
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lockdep_assert_held(&uncore->lock);
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if (GRAPHICS_VER(uncore->i915) >= 11) {
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if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) {
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/*
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* Always leave the hardware in multicast mode when doing reads
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* (see comment about Wa_22013088509 below) and only change it
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* to unicast mode when doing writes of a specific instance.
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*
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* No need to save old steering reg value.
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*/
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intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR,
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REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
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REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance) |
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(rw_flag == FW_REG_READ) ? GEN11_MCR_MULTICAST : 0);
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} else if (GRAPHICS_VER(uncore->i915) >= 11) {
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mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
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mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance);
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@ -202,26 +261,40 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
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*/
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if (rw_flag == FW_REG_WRITE)
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mcr_mask |= GEN11_MCR_MULTICAST;
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mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
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old_mcr = mcr;
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mcr &= ~mcr_mask;
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mcr |= mcr_ss;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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} else {
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mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
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mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance);
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mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
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old_mcr = mcr;
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mcr &= ~mcr_mask;
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mcr |= mcr_ss;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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}
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old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
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mcr &= ~mcr_mask;
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mcr |= mcr_ss;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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if (rw_flag == FW_REG_READ)
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val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
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else
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intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
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mcr &= ~mcr_mask;
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mcr |= old_mcr & mcr_mask;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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/*
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* For pre-MTL platforms, we need to restore the old value of the
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* steering control register to ensure that implicit steering continues
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* to behave as expected. For MTL and beyond, we need only reinstate
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* the 'multicast' bit (and only if we did a write that cleared it).
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*/
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if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE)
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intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
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else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70))
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, old_mcr);
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return val;
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}
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@ -296,6 +369,13 @@ void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 val
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void intel_gt_mcr_multicast_write(struct intel_gt *gt,
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i915_mcr_reg_t reg, u32 value)
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{
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/*
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* Ensure we have multicast behavior, just in case some non-i915 agent
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* left the hardware in unicast mode.
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*/
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if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
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intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
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intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
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}
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@ -312,6 +392,13 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt,
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*/
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void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)
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{
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/*
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* Ensure we have multicast behavior, just in case some non-i915 agent
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* left the hardware in unicast mode.
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*/
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if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
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intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
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intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
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}
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@ -389,6 +476,8 @@ static void get_nonterminated_steering(struct intel_gt *gt,
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enum intel_steering_type type,
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u8 *group, u8 *instance)
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{
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u32 dss;
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switch (type) {
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case L3BANK:
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*group = 0; /* unused */
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@ -412,6 +501,11 @@ static void get_nonterminated_steering(struct intel_gt *gt,
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*group = IS_DG2(gt->i915) ? 1 : 0;
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*instance = 0;
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break;
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case DSS:
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dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
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*group = dss / GEN_DSS_PER_GSLICE;
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*instance = dss % GEN_DSS_PER_GSLICE;
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break;
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case INSTANCE0:
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/*
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* There are a lot of MCR types for which instance (0, 0)
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@ -544,11 +638,20 @@ static void report_steering_type(struct drm_printer *p,
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void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
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bool dump_table)
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{
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drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n",
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gt->default_steering.groupid,
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gt->default_steering.instanceid);
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/*
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* Starting with MTL we no longer have default steering;
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* all ranges are explicitly steered.
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*/
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if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70))
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drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n",
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gt->default_steering.groupid,
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gt->default_steering.instanceid);
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if (IS_PONTEVECCHIO(gt->i915)) {
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if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
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for (int i = 0; i < NUM_STEERING_TYPES; i++)
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if (gt->steering_table[i])
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report_steering_type(p, gt, i, dump_table);
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} else if (IS_PONTEVECCHIO(gt->i915)) {
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report_steering_type(p, gt, INSTANCE0, dump_table);
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} else if (HAS_MSLICE_STEERING(gt->i915)) {
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report_steering_type(p, gt, MSLICE, dump_table);
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@ -56,6 +56,7 @@
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#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
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#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
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#define MTL_MCR_SELECTOR _MMIO(0xfd4)
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#define SF_MCR_SELECTOR _MMIO(0xfd8)
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#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
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#define GAM_MCR_SELECTOR _MMIO(0xfe0)
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@ -68,6 +69,8 @@
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#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
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#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
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#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
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#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
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#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
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#define IPEIR_I965 _MMIO(0x2064)
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#define IPEHR_I965 _MMIO(0x2068)
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@ -528,6 +531,8 @@
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#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
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/* Fuse readout registers for GT */
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#define XEHP_FUSE4 _MMIO(0x9114)
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#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
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#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
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#define GEN10_L3BANK_PAIR_COUNT 4
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#define GEN10_L3BANK_MASK 0x0F
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@ -60,6 +60,7 @@ enum intel_steering_type {
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MSLICE,
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LNCF,
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GAM,
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DSS,
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/*
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* On some platforms there are multiple types of MCR registers that
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@ -1128,18 +1128,23 @@ static void __set_mcr_steering(struct i915_wa_list *wal,
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wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
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}
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static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
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unsigned int slice, unsigned int subslice)
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static void debug_dump_steering(struct intel_gt *gt)
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{
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struct drm_printer p = drm_debug_printer("MCR Steering:");
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if (drm_debug_enabled(DRM_UT_DRIVER))
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intel_gt_mcr_report_steering(&p, gt, false);
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}
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static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
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unsigned int slice, unsigned int subslice)
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{
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__set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
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gt->default_steering.groupid = slice;
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gt->default_steering.instanceid = subslice;
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if (drm_debug_enabled(DRM_UT_DRIVER))
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intel_gt_mcr_report_steering(&p, gt, false);
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debug_dump_steering(gt);
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}
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static void
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@ -1581,12 +1586,30 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
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wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
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}
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static void
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xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
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{
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/* FIXME: Actual workarounds will be added in future patch(es) */
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/*
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* Unlike older platforms, we no longer setup implicit steering here;
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* all MCR accesses are explicitly steered.
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*/
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debug_dump_steering(gt);
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}
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static void
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gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = gt->i915;
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if (IS_PONTEVECCHIO(i915))
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/* FIXME: Media GT handling will be added in an upcoming patch */
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if (gt->type == GT_MEDIA)
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return;
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
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xelpg_gt_workarounds_init(gt, wal);
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else if (IS_PONTEVECCHIO(i915))
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pvc_gt_workarounds_init(gt, wal);
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else if (IS_DG2(i915))
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dg2_gt_workarounds_init(gt, wal);
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@ -1142,6 +1142,7 @@ static const struct intel_device_info mtl_info = {
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.display.has_modular_fia = 1,
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.extra_gt_list = xelpmp_extra_gt,
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.has_flat_ccs = 0,
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.has_mslice_steering = 0,
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.has_snoop = 1,
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.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
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.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
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