clocksource/drivers/timer-ti-dm: Simplify register access further
Let's unify register access and use dmtimer_read() and dmtimer_write() also for the timer revision specific registers like we now do for the shread registers. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-5-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -101,16 +101,16 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
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tidr = readl_relaxed(timer->io_base);
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tidr = readl_relaxed(timer->io_base);
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if (!(tidr >> 16)) {
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if (!(tidr >> 16)) {
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timer->revision = 1;
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timer->revision = 1;
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timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
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timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
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timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
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timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
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timer->func_base = timer->io_base;
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timer->func_base = timer->io_base;
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} else {
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} else {
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timer->revision = 2;
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timer->revision = 2;
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timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
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timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
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timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
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timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
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timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
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timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
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timer->pend = timer->io_base +
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timer->pend = timer->io_base +
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_OMAP_TIMER_WRITE_PEND_OFFSET +
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_OMAP_TIMER_WRITE_PEND_OFFSET +
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OMAP_TIMER_V2_FUNC_OFFSET;
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OMAP_TIMER_V2_FUNC_OFFSET;
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@ -165,13 +165,13 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
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}
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}
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/* Ack possibly pending interrupt */
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/* Ack possibly pending interrupt */
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writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
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dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
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}
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}
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static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
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static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
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unsigned int value)
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unsigned int value)
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{
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{
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writel_relaxed(value, timer->irq_ena);
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dmtimer_write(timer, timer->irq_ena, value);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
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}
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}
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@ -184,7 +184,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer)
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static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
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static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
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unsigned int value)
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unsigned int value)
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{
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{
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writel_relaxed(value, timer->irq_stat);
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dmtimer_write(timer, timer->irq_stat, value);
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}
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}
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static void omap_timer_restore_context(struct omap_dm_timer *timer)
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static void omap_timer_restore_context(struct omap_dm_timer *timer)
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@ -196,7 +196,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
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dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
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dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
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dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
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dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
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writel_relaxed(timer->context.tier, timer->irq_ena);
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dmtimer_write(timer, timer->irq_ena, timer->context.tier);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
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}
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}
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@ -208,7 +208,7 @@ static void omap_timer_save_context(struct omap_dm_timer *timer)
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timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
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timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
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timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
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timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
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timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
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timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
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timer->context.tier = readl_relaxed(timer->irq_ena);
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timer->context.tier = dmtimer_read(timer, timer->irq_ena);
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timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
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timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
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}
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}
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@ -722,9 +722,9 @@ static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
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omap_dm_timer_enable(timer);
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omap_dm_timer_enable(timer);
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if (timer->revision == 1)
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if (timer->revision == 1)
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l = readl_relaxed(timer->irq_ena) & ~mask;
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l = dmtimer_read(timer, timer->irq_ena) & ~mask;
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writel_relaxed(l, timer->irq_dis);
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dmtimer_write(timer, timer->irq_dis, l);
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l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
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l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
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@ -741,7 +741,7 @@ static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
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return 0;
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return 0;
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}
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}
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l = readl_relaxed(timer->irq_stat);
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l = dmtimer_read(timer, timer->irq_stat);
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return l;
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return l;
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}
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}
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@ -100,9 +100,9 @@ struct omap_dm_timer {
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struct clk *fclk;
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struct clk *fclk;
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void __iomem *io_base;
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void __iomem *io_base;
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void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
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int irq_stat; /* TISR/IRQSTATUS interrupt status */
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void __iomem *irq_ena; /* irq enable */
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int irq_ena; /* irq enable */
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void __iomem *irq_dis; /* irq disable, only on v2 ip */
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int irq_dis; /* irq disable, only on v2 ip */
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void __iomem *pend; /* write pending */
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void __iomem *pend; /* write pending */
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void __iomem *func_base; /* function register base */
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void __iomem *func_base; /* function register base */
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