cpufreq: tegra: Add support for Tegra210

This uses the DFLL clock support to enable CPU frequency scaling on
 Tegra210.
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Merge tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

cpufreq: tegra: Add support for Tegra210

This uses the DFLL clock support to enable CPU frequency scaling on
Tegra210.

* tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  cpufreq: dt-platdev: add Tegra210 to blacklist
  cpufreq: tegra124: extend to support Tegra210
  cpufreq: tegra124: do not handle the CPU rail

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 17:26:16 +01:00
commit f35635a6b7
3 changed files with 7 additions and 42 deletions

View File

@ -272,8 +272,8 @@ config ARM_TEGRA20_CPUFREQ
This adds the CPUFreq driver support for Tegra20 SOCs.
config ARM_TEGRA124_CPUFREQ
tristate "Tegra124 CPUFreq support"
depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR
bool "Tegra124 CPUFreq support"
depends on ARCH_TEGRA && CPUFREQ_DT
default y
help
This adds the CPUFreq driver support for Tegra124 SOCs.

View File

@ -119,6 +119,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "mediatek,mt8176", },
{ .compatible = "nvidia,tegra124", },
{ .compatible = "nvidia,tegra210", },
{ .compatible = "qcom,apq8096", },
{ .compatible = "qcom,msm8996", },

View File

@ -22,11 +22,9 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
#include <linux/types.h>
struct tegra124_cpufreq_priv {
struct regulator *vdd_cpu_reg;
struct clk *cpu_clk;
struct clk *pllp_clk;
struct clk *pllx_clk;
@ -60,14 +58,6 @@ out:
return ret;
}
static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
{
clk_set_parent(priv->cpu_clk, priv->pllp_clk);
clk_disable_unprepare(priv->dfll_clk);
regulator_sync_voltage(priv->vdd_cpu_reg);
clk_set_parent(priv->cpu_clk, priv->pllx_clk);
}
static int tegra124_cpufreq_probe(struct platform_device *pdev)
{
struct tegra124_cpufreq_priv *priv;
@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
if (!np)
return -ENODEV;
priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
if (IS_ERR(priv->vdd_cpu_reg)) {
ret = PTR_ERR(priv->vdd_cpu_reg);
goto out_put_np;
}
priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
if (IS_ERR(priv->cpu_clk)) {
ret = PTR_ERR(priv->cpu_clk);
goto out_put_vdd_cpu_reg;
goto out_put_np;
}
priv->dfll_clk = of_clk_get_by_name(np, "dfll");
@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
platform_device_register_full(&cpufreq_dt_devinfo);
if (IS_ERR(priv->cpufreq_dt_pdev)) {
ret = PTR_ERR(priv->cpufreq_dt_pdev);
goto out_switch_to_pllx;
goto out_put_pllp_clk;
}
platform_set_drvdata(pdev, priv);
return 0;
out_switch_to_pllx:
tegra124_cpu_switch_to_pllx(priv);
out_put_pllp_clk:
clk_put(priv->pllp_clk);
out_put_pllx_clk:
@ -146,34 +128,15 @@ out_put_dfll_clk:
clk_put(priv->dfll_clk);
out_put_cpu_clk:
clk_put(priv->cpu_clk);
out_put_vdd_cpu_reg:
regulator_put(priv->vdd_cpu_reg);
out_put_np:
of_node_put(np);
return ret;
}
static int tegra124_cpufreq_remove(struct platform_device *pdev)
{
struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
platform_device_unregister(priv->cpufreq_dt_pdev);
tegra124_cpu_switch_to_pllx(priv);
clk_put(priv->pllp_clk);
clk_put(priv->pllx_clk);
clk_put(priv->dfll_clk);
clk_put(priv->cpu_clk);
regulator_put(priv->vdd_cpu_reg);
return 0;
}
static struct platform_driver tegra124_cpufreq_platdrv = {
.driver.name = "cpufreq-tegra124",
.probe = tegra124_cpufreq_probe,
.remove = tegra124_cpufreq_remove,
};
static int __init tegra_cpufreq_init(void)
@ -181,7 +144,8 @@ static int __init tegra_cpufreq_init(void)
int ret;
struct platform_device *pdev;
if (!of_machine_is_compatible("nvidia,tegra124"))
if (!(of_machine_is_compatible("nvidia,tegra124") ||
of_machine_is_compatible("nvidia,tegra210")))
return -ENODEV;
/*