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[media] dt-bindings: Add a binding for Mediatek Video Decoder

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Add a DT binding documentation of Video Decoder for the
MT8173 SoC from Mediatek.

Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
Acked-by: Rob Herring <rob@kernel.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Tiffany Lin 2016-09-02 09:19:53 -03:00 committed by Mauro Carvalho Chehab
parent e2818a59f7
commit f3ad804c9d
1 changed files with 53 additions and 4 deletions
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57
Documentation/devicetree/bindings/media/mediatek-vcodec.txt
View File

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Mediatek Video Codec
Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
supports high resolution encoding functionalities.
supports high resolution encoding and decoding functionalities.
Required properties:
- compatible : "mediatek,mt8173-vcodec-enc" for encoder
"mediatek,mt8173-vcodec-dec" for decoder.
- reg : Physical base address of the video codec registers and length of
memory mapped region.
- interrupts : interrupt number to the cpu.
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property.
- clock-names: encoder must contain "venc_sel_src", "venc_sel",
- "venc_lt_sel_src", "venc_lt_sel".
- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
"venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
"univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
"venc_lt_sel", "vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
- mediatek,vpu : the node of video processor unit
Example:
vcodec_enc: vcodec@0x18002000 {
vcodec_dec: vcodec@16000000 {
compatible = "mediatek,mt8173-vcodec-dec";
reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
<0 0x16020000 0 0x1000>, /*VDEC_MISC*/
<0 0x16021000 0 0x800>, /*VDEC_LD*/
<0 0x16021800 0 0x800>, /*VDEC_TOP*/
<0 0x16022000 0 0x1000>, /*VDEC_CM*/
<0 0x16023000 0 0x1000>, /*VDEC_AD*/
<0 0x16024000 0 0x1000>, /*VDEC_AV*/
<0 0x16025000 0 0x1000>, /*VDEC_PP*/
<0 0x16026800 0 0x800>, /*VP8_VD*/
<0 0x16027000 0 0x800>, /*VP6_VD*/
<0 0x16027800 0 0x800>, /*VP8_VL*/
<0 0x16028400 0 0x400>; /*VP9_VD*/
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>,
<&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
clock-names = "vcodecpll",
"univpll_d2",
"clk_cci400_sel",
"vdec_sel",
"vdecpll",
"vencpll",
"venc_lt_sel",
"vdec_bus_clk_src";
};
vcodec_enc: vcodec@0x18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/