drm/amdgpu: Fix TLB invalidation request when using semaphore
[ Upstream commit 37c58ddf57364d1a636850bb8ba6acbe1e16195e ] Use a more meaningful variable name for the invalidation request that is distinct from the tmp variable that gets overwritten when acquiring the invalidation semaphore. Fixes: 4ed8a03740d0 ("drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10") Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -230,7 +230,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
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unsigned int vmhub, uint32_t flush_type)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
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u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);
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u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
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u32 tmp;
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/* Use register 17 for GART */
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const unsigned eng = 17;
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unsigned int i;
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@ -258,7 +259,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
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DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
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}
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WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
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WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
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/*
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* Issue a dummy read to wait for the ACK register to be cleared
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@ -487,13 +487,13 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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{
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bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
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const unsigned eng = 17;
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u32 j, tmp;
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u32 j, inv_req, tmp;
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struct amdgpu_vmhub *hub;
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BUG_ON(vmhub >= adev->num_vmhubs);
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hub = &adev->vmhub[vmhub];
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tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
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inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
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/* This is necessary for a HW workaround under SRIOV as well
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* as GFXOFF under bare metal
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@ -504,7 +504,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t req = hub->vm_inv_eng0_req + eng;
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uint32_t ack = hub->vm_inv_eng0_ack + eng;
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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return;
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}
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@ -532,7 +532,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
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}
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WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
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WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
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/*
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* Issue a dummy read to wait for the ACK register to be cleared
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