Merge series "Enable DMA mode on Intel Keem Bay platform" from Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>:
v2: Update patch to align with latest kernel release. v1: Initial patch version, to enable DMA mode on Intel Keembay platform. Michael Sit Wei Hong (2): dt-bindings: sound: intel, keembay-i2s: Add info for device to use DMA ASoC: Intel: KMB: Enable DMA transfer mode .../bindings/sound/intel,keembay-i2s.yaml | 14 ++ sound/soc/intel/Kconfig | 2 + sound/soc/intel/keembay/kmb_platform.c | 157 ++++++++++++++++-- sound/soc/intel/keembay/kmb_platform.h | 9 + 4 files changed, 167 insertions(+), 15 deletions(-) -- 2.17.1
This commit is contained in:
Mark Brown
commit
f3ddced14b
@ -45,6 +45,18 @@ properties:
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- const: osc
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- const: apb_clk
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dmas:
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items:
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- description: DMA controller phandle and DMA channel
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for TX and RX
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dma-names:
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items:
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- description: "tx" for the transmit channel
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"rx" for the receive channel
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- const: tx
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- const: rx
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required:
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- compatible
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- "#sound-dai-cells"
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@ -70,4 +82,6 @@ examples:
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "osc", "apb_clk";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_I2S3>, <&scmi_clk KEEM_BAY_PSS_I2S3>;
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dmas = <&axi_dma0 29 &axi_dma0 33>;
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dma-names = "tx", "rx";
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};
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@ -203,6 +203,8 @@ config SND_SOC_INTEL_KEEMBAY
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tristate "Keembay Platforms"
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depends on ARCH_KEEMBAY || COMPILE_TEST
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depends on COMMON_CLK
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select SND_DMAENGINE_PCM
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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If you have a Intel Keembay platform then enable this option
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by saying Y or m.
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@ -6,10 +6,12 @@
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//
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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@ -343,6 +345,53 @@ static const struct snd_soc_component_driver kmb_component = {
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.pointer = kmb_pcm_pointer,
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};
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static const struct snd_soc_component_driver kmb_component_dma = {
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.name = "kmb",
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};
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static int kmb_probe(struct snd_soc_dai *cpu_dai)
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{
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struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai);
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if (kmb_i2s->use_pio)
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return 0;
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snd_soc_dai_init_dma_data(cpu_dai, &kmb_i2s->play_dma_data,
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&kmb_i2s->capture_dma_data);
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return 0;
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}
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static inline void kmb_i2s_enable_dma(struct kmb_i2s_info *kmb_i2s, u32 stream)
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{
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u32 dma_reg;
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dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR);
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/* Enable DMA handshake for stream */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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dma_reg |= I2S_DMAEN_TXBLOCK;
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else
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dma_reg |= I2S_DMAEN_RXBLOCK;
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writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);
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}
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static inline void kmb_i2s_disable_dma(struct kmb_i2s_info *kmb_i2s, u32 stream)
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{
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u32 dma_reg;
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dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR);
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/* Disable DMA handshake for stream */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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dma_reg &= ~I2S_DMAEN_TXBLOCK;
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writel(1, kmb_i2s->i2s_base + I2S_RTXDMA);
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} else {
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dma_reg &= ~I2S_DMAEN_RXBLOCK;
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writel(1, kmb_i2s->i2s_base + I2S_RRXDMA);
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}
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writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);
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}
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static void kmb_i2s_start(struct kmb_i2s_info *kmb_i2s,
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struct snd_pcm_substream *substream)
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{
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@ -356,7 +405,11 @@ static void kmb_i2s_start(struct kmb_i2s_info *kmb_i2s,
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else
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writel(1, kmb_i2s->i2s_base + IRER);
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kmb_i2s_irq_trigger(kmb_i2s, substream->stream, config->chan_nr, true);
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if (kmb_i2s->use_pio)
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kmb_i2s_irq_trigger(kmb_i2s, substream->stream,
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config->chan_nr, true);
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else
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kmb_i2s_enable_dma(kmb_i2s, substream->stream);
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if (kmb_i2s->clock_provider)
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writel(1, kmb_i2s->i2s_base + CER);
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@ -434,7 +487,8 @@ static int kmb_dai_trigger(struct snd_pcm_substream *substream,
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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kmb_i2s->active--;
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kmb_i2s_stop(kmb_i2s, substream);
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if (kmb_i2s->use_pio)
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kmb_i2s_stop(kmb_i2s, substream);
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break;
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default:
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return -EINVAL;
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@ -485,16 +539,22 @@ static int kmb_dai_hw_params(struct snd_pcm_substream *substream,
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config->data_width = 16;
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kmb_i2s->ccr = 0x00;
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kmb_i2s->xfer_resolution = 0x02;
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kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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config->data_width = 32;
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kmb_i2s->ccr = 0x14;
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kmb_i2s->xfer_resolution = 0x05;
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kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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config->data_width = 32;
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kmb_i2s->ccr = 0x10;
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kmb_i2s->xfer_resolution = 0x05;
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kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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default:
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dev_err(kmb_i2s->dev, "kmb: unsupported PCM fmt");
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@ -572,9 +632,56 @@ static int kmb_dai_prepare(struct snd_pcm_substream *substream,
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return 0;
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}
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static int kmb_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai);
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struct snd_dmaengine_dai_dma_data *dma_data;
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if (kmb_i2s->use_pio)
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return 0;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dma_data = &kmb_i2s->play_dma_data;
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else
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dma_data = &kmb_i2s->capture_dma_data;
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snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
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return 0;
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}
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static int kmb_dai_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai);
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/* I2S Programming sequence in Keem_Bay_VPU_DB_v1.1 */
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if (kmb_i2s->use_pio)
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kmb_i2s_clear_irqs(kmb_i2s, substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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writel(0, kmb_i2s->i2s_base + ITER);
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else
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writel(0, kmb_i2s->i2s_base + IRER);
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if (kmb_i2s->use_pio)
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kmb_i2s_irq_trigger(kmb_i2s, substream->stream, 8, false);
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else
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kmb_i2s_disable_dma(kmb_i2s, substream->stream);
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if (!kmb_i2s->active) {
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writel(0, kmb_i2s->i2s_base + CER);
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writel(0, kmb_i2s->i2s_base + IER);
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}
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return 0;
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}
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static struct snd_soc_dai_ops kmb_dai_ops = {
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.startup = kmb_dai_startup,
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.trigger = kmb_dai_trigger,
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.hw_params = kmb_dai_hw_params,
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.hw_free = kmb_dai_hw_free,
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.prepare = kmb_dai_prepare,
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.set_fmt = kmb_set_dai_fmt,
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};
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@ -607,6 +714,7 @@ static struct snd_soc_dai_driver intel_kmb_i2s_dai[] = {
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SNDRV_PCM_FMTBIT_S16_LE),
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},
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.ops = &kmb_dai_ops,
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.probe = kmb_probe,
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},
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};
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@ -626,6 +734,7 @@ static struct snd_soc_dai_driver intel_kmb_tdm_dai[] = {
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SNDRV_PCM_FMTBIT_S16_LE),
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},
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.ops = &kmb_dai_ops,
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.probe = kmb_probe,
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},
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};
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@ -637,10 +746,12 @@ static const struct of_device_id kmb_plat_of_match[] = {
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static int kmb_plat_dai_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct snd_soc_dai_driver *kmb_i2s_dai;
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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struct kmb_i2s_info *kmb_i2s;
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struct resource *res;
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int ret, irq;
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u32 comp1_reg;
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@ -682,7 +793,7 @@ static int kmb_plat_dai_probe(struct platform_device *pdev)
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return PTR_ERR(kmb_i2s->clk_i2s);
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}
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kmb_i2s->i2s_base = devm_platform_ioremap_resource(pdev, 0);
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kmb_i2s->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(kmb_i2s->i2s_base))
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return PTR_ERR(kmb_i2s->i2s_base);
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@ -692,22 +803,38 @@ static int kmb_plat_dai_probe(struct platform_device *pdev)
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kmb_i2s->dev = &pdev->dev;
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irq = platform_get_irq_optional(pdev, 0);
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if (irq > 0) {
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ret = devm_request_irq(dev, irq, kmb_i2s_irq_handler, 0,
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pdev->name, kmb_i2s);
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if (ret < 0) {
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dev_err(dev, "failed to request irq\n");
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return ret;
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}
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}
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comp1_reg = readl(kmb_i2s->i2s_base + I2S_COMP_PARAM_1);
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kmb_i2s->fifo_th = (1 << COMP1_FIFO_DEPTH(comp1_reg)) / 2;
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ret = devm_snd_soc_register_component(dev, &kmb_component,
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kmb_i2s_dai, 1);
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kmb_i2s->use_pio = !(of_property_read_bool(np, "dmas"));
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if (kmb_i2s->use_pio) {
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irq = platform_get_irq_optional(pdev, 0);
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if (irq > 0) {
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ret = devm_request_irq(dev, irq, kmb_i2s_irq_handler, 0,
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pdev->name, kmb_i2s);
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if (ret < 0) {
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dev_err(dev, "failed to request irq\n");
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return ret;
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}
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}
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ret = devm_snd_soc_register_component(dev, &kmb_component,
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kmb_i2s_dai, 1);
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} else {
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kmb_i2s->play_dma_data.addr = res->start + I2S_TXDMA;
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kmb_i2s->capture_dma_data.addr = res->start + I2S_RXDMA;
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ret = snd_dmaengine_pcm_register(&pdev->dev,
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NULL, 0);
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if (ret) {
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dev_err(&pdev->dev, "could not register dmaengine: %d\n",
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ret);
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return ret;
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}
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ret = devm_snd_soc_register_component(dev, &kmb_component_dma,
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kmb_i2s_dai, 1);
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}
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if (ret) {
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dev_err(dev, "not able to register dai\n");
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return ret;
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@ -12,6 +12,7 @@
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include <sound/dmaengine_pcm.h>
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/* Register values with reference to KMB databook v1.1 */
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/* common register for all channel */
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@ -103,7 +104,12 @@
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#define DW_I2S_PROVIDER BIT(3)
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#define I2S_RXDMA 0x01C0
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#define I2S_RRXDMA 0x01C4
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#define I2S_TXDMA 0x01C8
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#define I2S_RTXDMA 0x01CC
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#define I2S_DMACR 0x0200
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#define I2S_DMAEN_RXBLOCK (1 << 16)
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#define I2S_DMAEN_TXBLOCK (1 << 17)
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/*
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* struct i2s_clk_config_data - represent i2s clk configuration data
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@ -131,6 +137,9 @@ struct kmb_i2s_info {
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u32 xfer_resolution;
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u32 fifo_th;
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bool clock_provider;
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/* data related to DMA transfers b/w i2s and DMAC */
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struct snd_dmaengine_dai_dma_data play_dma_data;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct i2s_clk_config_data config;
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int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
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