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arm64: dts: imx8mm: Add cpu speed grading and all OPPs

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Add a nvmem cell on cpu node referencing speed grade and the 1.8 Ghz
cpufreq opp.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Leonard Crestez 2019-05-13 11:01:41 +00:00 committed by Shawn Guo
parent 78cc25fa26
commit f403a26c86
1 changed files with 16 additions and 1 deletions
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17
arch/arm64/boot/dts/freescale/imx8mm.dtsi
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@ -53,6 +53,8 @@
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>; operating-points-v2 = <&a53_opp_table>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
}; };
A53_1: cpu@1 { A53_1: cpu@1 {
@ -100,14 +102,23 @@
opp-1200000000 { opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>; opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000>; opp-microvolt = <850000>;
opp-supported-hw = <0xe>, <0x7>;
clock-latency-ns = <150000>; clock-latency-ns = <150000>;
}; };
opp-1600000000 { opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>; opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>; opp-microvolt = <900000>;
opp-supported-hw = <0xc>, <0x7>;
clock-latency-ns = <150000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
/* Consumer only but rely on speed grading */
opp-supported-hw = <0x8>, <0x7>;
clock-latency-ns = <150000>; clock-latency-ns = <150000>;
opp-suspend;
}; };
}; };
@ -319,6 +330,10 @@
/* For nvmem subnodes */ /* For nvmem subnodes */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
}; };
anatop: anatop@30360000 { anatop: anatop@30360000 {