arm64: KVM: GICv3: move system register access to msr_s/mrs_s
Commit 72c5839515 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the occurences used by KVM as the code wasn't
merged yet.
Just fix the accessors.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Marc Zyngier
Christoffer Dall
parent
d329de0933
commit
f4c321eb26
@ -48,11 +48,11 @@
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dsb st
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// Save all interesting registers
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mrs x4, ICH_HCR_EL2
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mrs x5, ICH_VMCR_EL2
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mrs x6, ICH_MISR_EL2
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mrs x7, ICH_EISR_EL2
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mrs x8, ICH_ELSR_EL2
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mrs_s x4, ICH_HCR_EL2
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mrs_s x5, ICH_VMCR_EL2
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mrs_s x6, ICH_MISR_EL2
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mrs_s x7, ICH_EISR_EL2
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mrs_s x8, ICH_ELSR_EL2
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str w4, [x3, #VGIC_V3_CPU_HCR]
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str w5, [x3, #VGIC_V3_CPU_VMCR]
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@ -60,9 +60,9 @@
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str w7, [x3, #VGIC_V3_CPU_EISR]
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str w8, [x3, #VGIC_V3_CPU_ELRSR]
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msr ICH_HCR_EL2, xzr
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msr_s ICH_HCR_EL2, xzr
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mrs x21, ICH_VTR_EL2
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mrs_s x21, ICH_VTR_EL2
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mvn w22, w21
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ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4
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@ -71,22 +71,22 @@
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br x24
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1:
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mrs x20, ICH_LR15_EL2
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mrs x19, ICH_LR14_EL2
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mrs x18, ICH_LR13_EL2
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mrs x17, ICH_LR12_EL2
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mrs x16, ICH_LR11_EL2
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mrs x15, ICH_LR10_EL2
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mrs x14, ICH_LR9_EL2
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mrs x13, ICH_LR8_EL2
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mrs x12, ICH_LR7_EL2
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mrs x11, ICH_LR6_EL2
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mrs x10, ICH_LR5_EL2
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mrs x9, ICH_LR4_EL2
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mrs x8, ICH_LR3_EL2
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mrs x7, ICH_LR2_EL2
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mrs x6, ICH_LR1_EL2
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mrs x5, ICH_LR0_EL2
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mrs_s x20, ICH_LR15_EL2
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mrs_s x19, ICH_LR14_EL2
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mrs_s x18, ICH_LR13_EL2
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mrs_s x17, ICH_LR12_EL2
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mrs_s x16, ICH_LR11_EL2
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mrs_s x15, ICH_LR10_EL2
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mrs_s x14, ICH_LR9_EL2
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mrs_s x13, ICH_LR8_EL2
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mrs_s x12, ICH_LR7_EL2
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mrs_s x11, ICH_LR6_EL2
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mrs_s x10, ICH_LR5_EL2
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mrs_s x9, ICH_LR4_EL2
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mrs_s x8, ICH_LR3_EL2
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mrs_s x7, ICH_LR2_EL2
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mrs_s x6, ICH_LR1_EL2
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mrs_s x5, ICH_LR0_EL2
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adr x24, 1f
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add x24, x24, x23
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@ -113,34 +113,34 @@
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs x20, ICH_AP0R3_EL2
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mrs_s x20, ICH_AP0R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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mrs x19, ICH_AP0R2_EL2
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mrs_s x19, ICH_AP0R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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6: mrs x18, ICH_AP0R1_EL2
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6: mrs_s x18, ICH_AP0R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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5: mrs x17, ICH_AP0R0_EL2
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5: mrs_s x17, ICH_AP0R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP0R]
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs x20, ICH_AP1R3_EL2
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mrs_s x20, ICH_AP1R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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mrs x19, ICH_AP1R2_EL2
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mrs_s x19, ICH_AP1R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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6: mrs x18, ICH_AP1R1_EL2
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6: mrs_s x18, ICH_AP1R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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5: mrs x17, ICH_AP1R0_EL2
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5: mrs_s x17, ICH_AP1R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP1R]
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// Restore SRE_EL1 access and re-enable SRE at EL1.
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mrs x5, ICC_SRE_EL2
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mrs_s x5, ICC_SRE_EL2
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orr x5, x5, #ICC_SRE_EL2_ENABLE
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msr ICC_SRE_EL2, x5
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msr_s ICC_SRE_EL2, x5
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isb
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mov x5, #1
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msr ICC_SRE_EL1, x5
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msr_s ICC_SRE_EL1, x5
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.endm
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/*
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@ -150,7 +150,7 @@
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.macro restore_vgic_v3_state
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// Disable SRE_EL1 access. Necessary, otherwise
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// ICH_VMCR_EL2.VFIQEn becomes one, and FIQ happens...
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msr ICC_SRE_EL1, xzr
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msr_s ICC_SRE_EL1, xzr
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isb
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// Compute the address of struct vgic_cpu
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@ -160,34 +160,34 @@
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ldr w4, [x3, #VGIC_V3_CPU_HCR]
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ldr w5, [x3, #VGIC_V3_CPU_VMCR]
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msr ICH_HCR_EL2, x4
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msr ICH_VMCR_EL2, x5
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msr_s ICH_HCR_EL2, x4
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msr_s ICH_VMCR_EL2, x5
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mrs x21, ICH_VTR_EL2
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mrs_s x21, ICH_VTR_EL2
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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msr ICH_AP1R3_EL2, x20
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msr_s ICH_AP1R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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msr ICH_AP1R2_EL2, x19
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msr_s ICH_AP1R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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msr ICH_AP1R1_EL2, x18
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msr_s ICH_AP1R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
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msr ICH_AP1R0_EL2, x17
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msr_s ICH_AP1R0_EL2, x17
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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msr ICH_AP0R3_EL2, x20
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msr_s ICH_AP0R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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msr ICH_AP0R2_EL2, x19
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msr_s ICH_AP0R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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msr ICH_AP0R1_EL2, x18
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msr_s ICH_AP0R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
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msr ICH_AP0R0_EL2, x17
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msr_s ICH_AP0R0_EL2, x17
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and w22, w21, #0xf
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mvn w22, w21
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@ -220,22 +220,22 @@
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br x24
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1:
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msr ICH_LR15_EL2, x20
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msr ICH_LR14_EL2, x19
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msr ICH_LR13_EL2, x18
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msr ICH_LR12_EL2, x17
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msr ICH_LR11_EL2, x16
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msr ICH_LR10_EL2, x15
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msr ICH_LR9_EL2, x14
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msr ICH_LR8_EL2, x13
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msr ICH_LR7_EL2, x12
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msr ICH_LR6_EL2, x11
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msr ICH_LR5_EL2, x10
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msr ICH_LR4_EL2, x9
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msr ICH_LR3_EL2, x8
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msr ICH_LR2_EL2, x7
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msr ICH_LR1_EL2, x6
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msr ICH_LR0_EL2, x5
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msr_s ICH_LR15_EL2, x20
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msr_s ICH_LR14_EL2, x19
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msr_s ICH_LR13_EL2, x18
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msr_s ICH_LR12_EL2, x17
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msr_s ICH_LR11_EL2, x16
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msr_s ICH_LR10_EL2, x15
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msr_s ICH_LR9_EL2, x14
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msr_s ICH_LR8_EL2, x13
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msr_s ICH_LR7_EL2, x12
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msr_s ICH_LR6_EL2, x11
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msr_s ICH_LR5_EL2, x10
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msr_s ICH_LR4_EL2, x9
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msr_s ICH_LR3_EL2, x8
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msr_s ICH_LR2_EL2, x7
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msr_s ICH_LR1_EL2, x6
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msr_s ICH_LR0_EL2, x5
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// Ensure that the above will have reached the
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// (re)distributors. This ensure the guest will read
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@ -244,9 +244,9 @@
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dsb sy
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// Prevent the guest from touching the GIC system registers
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mrs x5, ICC_SRE_EL2
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mrs_s x5, ICC_SRE_EL2
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and x5, x5, #~ICC_SRE_EL2_ENABLE
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msr ICC_SRE_EL2, x5
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msr_s ICC_SRE_EL2, x5
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.endm
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ENTRY(__save_vgic_v3_state)
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@ -260,7 +260,7 @@ ENTRY(__restore_vgic_v3_state)
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ENDPROC(__restore_vgic_v3_state)
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ENTRY(__vgic_v3_get_ich_vtr_el2)
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mrs x0, ICH_VTR_EL2
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mrs_s x0, ICH_VTR_EL2
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ret
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ENDPROC(__vgic_v3_get_ich_vtr_el2)
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