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net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail

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1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Fixes: 9992f37e34 ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Biao Huang 2019-05-24 14:26:09 +08:00 committed by David S. Miller
parent 5e7f7fc538
commit f4ca7a9260
1 changed files with 0 additions and 2 deletions
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2
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
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@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
return PTR_ERR(plat_dat);
plat_dat->interface = priv_plat->phy_mode;
/* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
plat_dat->clk_csr = 5;
plat_dat->has_gmac4 = 1;
plat_dat->has_gmac = 0;
plat_dat->pmt = 0;