drm/amdgpu: force enable gfx ras for vega20 ws
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -33,6 +33,7 @@
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#include "amdgpu_atomfirmware.h"
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#include "amdgpu_xgmi.h"
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#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
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#include "atom.h"
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static const char *RAS_FS_NAME = "ras";
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@ -2063,6 +2064,24 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
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adev->asic_type == CHIP_SIENNA_CICHLID;
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}
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/*
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* this is workaround for vega20 workstation sku,
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* force enable gfx ras, ignore vbios gfx ras flag
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* due to GC EDC can not write
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*/
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static void amdgpu_ras_get_quirks(struct amdgpu_device *adev,
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uint32_t *hw_supported)
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{
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struct atom_context *ctx = adev->mode_info.atom_context;
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if (!ctx)
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return;
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if (strnstr(ctx->vbios_version, "D16406",
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sizeof(ctx->vbios_version)))
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*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX);
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}
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/*
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* check hardware's ras ability which will be saved in hw_supported.
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* if hardware does not support ras, we can skip some ras initializtion and
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@ -2106,6 +2125,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
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1 << AMDGPU_RAS_BLOCK__MMHUB);
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}
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amdgpu_ras_get_quirks(adev, hw_supported);
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/* hw_supported needs to be aligned with RAS block mask. */
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*hw_supported &= AMDGPU_RAS_BLOCK_MASK;
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