arm64: dts: freescale: add i.MX8DXL SoC support
i.MX8DXL is a device targeting the automotive and industrial market segments. The chip is designed to achieve both high performance and low power consumption. It has a dual (2x) Cortex-A35 processor. This patch adds the basic support for i.MX8DXL SoC. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Shenwei Wang
Shawn Guo
52
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
Normal file
52
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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&audio_ipg_clk {
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clock-frequency = <160000000>;
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};
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&dma_ipg_clk {
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clock-frequency = <160000000>;
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};
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&i2c0 {
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compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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};
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&i2c1 {
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compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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};
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&i2c2 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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};
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&i2c3 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpuart0 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpuart1 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpuart2 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpuart3 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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};
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142
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
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142
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
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@ -0,0 +1,142 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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/delete-node/ &enet1_lpcg;
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/delete-node/ &fec2;
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&conn_subsys {
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conn_enet0_root_clk: clock-conn-enet0-root {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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clock-output-names = "conn_enet0_root_clk";
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};
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eqos: ethernet@5b050000 {
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compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
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reg = <0x5b050000 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eth_wake_irq", "macirq";
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clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
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<&eqos_lpcg IMX_LPCG_CLK_6>,
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<&eqos_lpcg IMX_LPCG_CLK_0>,
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<&eqos_lpcg IMX_LPCG_CLK_5>,
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<&eqos_lpcg IMX_LPCG_CLK_2>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
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assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <125000000>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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status = "disabled";
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};
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usbotg2: usb@5b0e0000 {
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compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
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reg = <0x5b0e0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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fsl,usbphy = <&usbphy2>;
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fsl,usbmisc = <&usbmisc2 0>;
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/*
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* usbotg1 and usbotg2 share one clcok.
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* scu firmware disables the access to the clock and keeps
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* it always on in case other core (M4) uses one of these.
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*/
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clocks = <&clk_dummy>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>;
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rx-burst-size-dword = <0x10>;
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#stream-id-cells = <1>;
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power-domains = <&pd IMX_SC_R_USB_1>;
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status = "disabled";
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clk_dummy: clock-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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};
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usbmisc2: usbmisc@5b0e0200 {
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#index-cells = <1>;
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compatible = "fsl,imx7ulp-usbmisc";
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reg = <0x5b0e0200 0x200>;
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};
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usbphy2: usbphy@0x5b110000 {
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compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
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reg = <0x5b110000 0x1000>;
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clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
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power-domains = <&pd IMX_SC_R_USB_1_PHY>;
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status = "disabled";
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};
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eqos_lpcg: clock-controller@5b240000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b240000 0x10000>;
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#clock-cells = <1>;
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clocks = <&conn_enet0_root_clk>,
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<&conn_axi_clk>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "eqos_ptp",
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"eqos_mem_clk",
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"eqos_aclk",
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"eqos_clk",
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"eqos_csr_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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usb2_2_lpcg: clock-controller@5b280000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b280000 0x10000>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_7>;
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clocks = <&conn_ipg_clk>;
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clock-output-names = "usboh3_2_phy_ipg_clk";
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power-domains = <&pd IMX_SC_R_USB_1_PHY>;
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};
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};
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&enet0_lpcg {
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clocks = <&conn_enet0_root_clk>,
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<&conn_enet0_root_clk>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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};
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&fec1 {
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compatible = "fsl,imx8qm-fec";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <125000000>;
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};
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&usdhc1 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usdhc2 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usdhc3 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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};
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9
arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
Normal file
9
arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
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@ -0,0 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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&ddr_pmu0 {
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compatible = "fsl,imx8-ddr-pmu";
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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74
arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
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74
arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
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@ -0,0 +1,74 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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&lsio_gpio0 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio1 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio2 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio3 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio4 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio5 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio6 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_gpio7 {
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compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu0 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu1 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu2 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu3 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu4 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lsio_mu5 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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};
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238
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
Normal file
238
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
Normal file
@ -0,0 +1,238 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/pads-imx8dxl.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &eqos;
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gpio0 = &lsio_gpio0;
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gpio1 = &lsio_gpio1;
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gpio2 = &lsio_gpio2;
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gpio3 = &lsio_gpio3;
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gpio4 = &lsio_gpio4;
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gpio5 = &lsio_gpio5;
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gpio6 = &lsio_gpio6;
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gpio7 = &lsio_gpio7;
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mu1 = &lsio_mu1;
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};
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cpus: cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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/* We have 1 clusters with 2 Cortex-A35 cores */
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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#cooling-cells = <2>;
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operating-points-v2 = <&a35_opp_table>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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#cooling-cells = <2>;
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operating-points-v2 = <&a35_opp_table>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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a35_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
|
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
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reserved-memory {
|
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#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
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dsp_reserved: dsp@92400000 {
|
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reg = <0 0x92400000 0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
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|
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pmu {
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compatible = "arm,armv8-pmuv3";
|
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
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|
||||
psci {
|
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compatible = "arm,psci-1.0";
|
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method = "smc";
|
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};
|
||||
|
||||
system-controller {
|
||||
compatible = "fsl,imx-scu";
|
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mbox-names = "tx0",
|
||||
"rx0",
|
||||
"gip3";
|
||||
mboxes = <&lsio_mu1 0 0
|
||||
&lsio_mu1 1 0
|
||||
&lsio_mu1 3 3>;
|
||||
|
||||
pd: power-controller {
|
||||
compatible = "fsl,scu-pd";
|
||||
#power-domain-cells = <1>;
|
||||
wakeup-irq = <160 163 235 236 237 228 229 230 231 238
|
||||
239 240 166 169>;
|
||||
};
|
||||
|
||||
clk: clock-controller {
|
||||
compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
|
||||
#clock-cells = <2>;
|
||||
clocks = <&xtal32k &xtal24m>;
|
||||
clock-names = "xtal_32KHz", "xtal_24Mhz";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl {
|
||||
compatible = "fsl,imx8dxl-iomuxc";
|
||||
};
|
||||
|
||||
ocotp: ocotp {
|
||||
compatible = "fsl,imx8qxp-scu-ocotp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
fec_mac0: mac@2c4 {
|
||||
reg = <0x2c4 6>;
|
||||
};
|
||||
|
||||
fec_mac1: mac@2c6 {
|
||||
reg = <0x2c6 6>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fsl,imx8qxp-sc-rtc";
|
||||
};
|
||||
|
||||
sc_pwrkey: keys {
|
||||
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "fsl,imx-sc-wdt";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "fsl,imx-sc-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
cpu-thermal0 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <107000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <127000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* The two values below cannot be changed by the board */
|
||||
xtal32k: clock-xtal32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xtal_32KHz";
|
||||
};
|
||||
|
||||
xtal24m: clock-xtal24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xtal_24MHz";
|
||||
};
|
||||
|
||||
/* sorted in register address */
|
||||
#include "imx8-ss-adma.dtsi"
|
||||
#include "imx8-ss-conn.dtsi"
|
||||
#include "imx8-ss-ddr.dtsi"
|
||||
#include "imx8-ss-lsio.dtsi"
|
||||
};
|
||||
|
||||
#include "imx8dxl-ss-adma.dtsi"
|
||||
#include "imx8dxl-ss-conn.dtsi"
|
||||
#include "imx8dxl-ss-lsio.dtsi"
|
||||
#include "imx8dxl-ss-ddr.dtsi"
|
||||
Reference in New Issue
Block a user