bnx2x: Supporting PHY FW upgrade
There are 3 operations that the driver needs to support to allow applications to access the PHY FW (on top of the MDC/MDIO access). Since those are essentially nvram access commands, adding them to the ethtool -E interface. Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
01cd452846
commit
f57a60256d
@ -1996,7 +1996,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
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/*****************************************************************************/
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/* External Phy section */
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/*****************************************************************************/
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static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
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void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
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{
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
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MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
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@ -2035,7 +2035,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
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params->port);
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/* HW reset */
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bnx2x_hw_reset(bp, params->port);
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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@ -2106,8 +2106,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
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params->port);
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/* HW reset */
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bnx2x_hw_reset(bp, params->port);
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bnx2x_ext_phy_hw_reset(bp, params->port);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
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@ -2118,7 +2117,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
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params->port);
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/* HW reset */
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bnx2x_hw_reset(bp, params->port);
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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@ -2146,7 +2145,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
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case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
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DP(NETIF_MSG_LINK, "SerDes 5482\n");
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bnx2x_hw_reset(bp, params->port);
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bnx2x_ext_phy_hw_reset(bp, params->port);
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break;
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default:
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@ -6573,7 +6572,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
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swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
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swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
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bnx2x_hw_reset(bp, 1 ^ (swap_val && swap_override));
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bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
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msleep(5);
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if (swap_val && swap_override)
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@ -6647,7 +6646,7 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
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(1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
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REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
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bnx2x_hw_reset(bp, 1);
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bnx2x_ext_phy_hw_reset(bp, 1);
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msleep(5);
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for (port = 0; port < PORT_MAX; port++) {
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/* Extract the ext phy address for the port */
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@ -6714,9 +6713,7 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
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return rc;
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}
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static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
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void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
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{
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u16 val, cnt;
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@ -7032,7 +7029,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
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for (cnt = 0; cnt < 100; cnt++)
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msleep(5);
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bnx2x_hw_reset(bp, port);
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bnx2x_ext_phy_hw_reset(bp, port);
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for (cnt = 0; cnt < 100; cnt++)
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msleep(5);
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@ -187,6 +187,10 @@ u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
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/* One-time initialization for external phy after power up */
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u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
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/* Reset the external PHY using GPIO */
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void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
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void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr);
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u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
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u8 byte_cnt, u8 *o_buf);
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@ -9353,7 +9353,8 @@ static int bnx2x_set_eeprom(struct net_device *dev,
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struct ethtool_eeprom *eeprom, u8 *eebuf)
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{
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struct bnx2x *bp = netdev_priv(dev);
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int rc;
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int port = BP_PORT(bp);
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int rc = 0;
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if (!netif_running(dev))
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return -EAGAIN;
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@ -9365,27 +9366,62 @@ static int bnx2x_set_eeprom(struct net_device *dev,
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/* parameters already validated in ethtool_set_eeprom */
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/* If the magic number is PHY (0x00504859) upgrade the PHY FW */
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if (eeprom->magic == 0x00504859)
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if (bp->port.pmf) {
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/* PHY eeprom can be accessed only by the PMF */
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if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
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!bp->port.pmf)
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return -EINVAL;
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if (eeprom->magic == 0x50485950) {
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/* 'PHYP' (0x50485950): prepare phy for FW upgrade */
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bnx2x_stats_handle(bp, STATS_EVENT_STOP);
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bnx2x_acquire_phy_lock(bp);
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rc |= bnx2x_link_reset(&bp->link_params,
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&bp->link_vars, 0);
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if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
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MISC_REGISTERS_GPIO_HIGH, port);
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bnx2x_release_phy_lock(bp);
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bnx2x_link_report(bp);
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} else if (eeprom->magic == 0x50485952) {
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/* 'PHYR' (0x50485952): re-init link after FW upgrade */
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if ((bp->state == BNX2X_STATE_OPEN) ||
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(bp->state == BNX2X_STATE_DISABLED)) {
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bnx2x_acquire_phy_lock(bp);
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rc |= bnx2x_link_reset(&bp->link_params,
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&bp->link_vars, 1);
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rc |= bnx2x_phy_init(&bp->link_params,
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&bp->link_vars);
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bnx2x_release_phy_lock(bp);
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bnx2x_calc_fc_adv(bp);
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}
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} else if (eeprom->magic == 0x53985943) {
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/* 'PHYC' (0x53985943): PHY FW upgrade completed */
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if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
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u8 ext_phy_addr =
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(bp->link_params.ext_phy_config &
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT;
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/* DSP Remove Download Mode */
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
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MISC_REGISTERS_GPIO_LOW, port);
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_flash_download(bp, BP_PORT(bp),
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bp->link_params.ext_phy_config,
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(bp->state != BNX2X_STATE_CLOSED),
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eebuf, eeprom->len);
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if ((bp->state == BNX2X_STATE_OPEN) ||
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(bp->state == BNX2X_STATE_DISABLED)) {
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rc |= bnx2x_link_reset(&bp->link_params,
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&bp->link_vars, 1);
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rc |= bnx2x_phy_init(&bp->link_params,
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&bp->link_vars);
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}
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bnx2x_release_phy_lock(bp);
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} else /* Only the PMF can access the PHY */
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return -EINVAL;
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else
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bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
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/* wait 0.5 sec to allow it to run */
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msleep(500);
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bnx2x_ext_phy_hw_reset(bp, port);
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msleep(500);
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bnx2x_release_phy_lock(bp);
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}
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} else
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rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
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return rc;
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