wifi: rtw89: 8922a: add set_channel BB part
In additional to configure band, channel and bandwidth registers, it also configure CCK support on 2GHZ band, spur elimination, and RX gain. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240215055741.14148-3-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
ca1e116388
commit
f59cb1a030
@ -8448,6 +8448,9 @@
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#define B_PATH1_5MDET_SB2 BIT(8)
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#define B_PATH1_5MDET_SB0 BIT(6)
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#define B_PATH1_5MDET_TH GENMASK(5, 0)
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#define R_S0S1_CSI_WGT 0x4D34
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#define B_S0S1_CSI_WGT_EN BIT(0)
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#define B_S0S1_CSI_WGT_TONE_IDX GENMASK(31, 20)
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#define R_CHINFO_ELM_SRC 0x4D84
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#define B_CHINFO_ELM_BITMAP GENMASK(22, 0)
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#define B_CHINFO_SRC GENMASK(31, 30)
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@ -8601,18 +8604,48 @@
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#define B_S0_DACKQ8_K GENMASK(15, 8)
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#define R_DCFO_WEIGHT_V1 0x6244
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#define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28)
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#define R_DAC_CLK 0x625C
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#define B_DAC_CLK GENMASK(31, 30)
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#define R_DCFO_OPT_V1 0x6260
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#define B_DCFO_OPT_EN_V1 BIT(17)
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#define R_TXFCTR 0x627C
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#define B_TXFCTR_THD GENMASK(19, 10)
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#define R_TXSCALE 0x6284
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#define B_TXFCTR_EN BIT(19)
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#define R_PCOEFF01 0x6684
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#define B_PCOEFF01 GENMASK(23, 0)
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#define R_PCOEFF23 0x6688
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#define B_PCOEFF23 GENMASK(23, 0)
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#define R_PCOEFF45 0x668c
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#define B_PCOEFF45 GENMASK(23, 0)
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#define R_PCOEFF67 0x6690
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#define B_PCOEFF67 GENMASK(23, 0)
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#define R_PCOEFF89 0x6694
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#define B_PCOEFF89 GENMASK(23, 0)
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#define R_PCOEFFAB 0x6698
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#define B_PCOEFFAB GENMASK(23, 0)
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#define R_PCOEFFCD 0x669c
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#define B_PCOEFFCD GENMASK(23, 0)
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#define R_PCOEFFEF 0x66a0
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#define B_PCOEFFEF GENMASK(23, 0)
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#define R_MGAIN_BIAS 0x672c
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#define B_MGAIN_BIAS_BW20 GENMASK(3, 0)
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#define B_MGAIN_BIAS_BW40 GENMASK(7, 4)
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#define R_CCK_RPL_OFST 0x6750
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#define B_CCK_RPL_OFST GENMASK(7, 0)
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#define R_BK_FC0INV 0x6758
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#define B_BK_FC0INV GENMASK(18, 0)
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#define R_CCK_FC0INV 0x675c
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#define B_CCK_FC0INV GENMASK(18, 0)
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#define R_SEG0R_EDCCA_LVL_BE 0x69EC
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#define R_SEG0R_PPDU_LVL_BE 0x69F0
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#define R_SEGSND 0x6A14
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#define B_SEGSND_EN BIT(31)
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#define R_DBCC 0x6B48
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#define B_DBCC_EN BIT(0)
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#define R_FC0 0x6B4C
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#define B_BW40_2XFFT BIT(31)
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#define B_FC0 GENMASK(12, 0)
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#define R_FC0INV_SBW 0x6B50
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#define B_SMALLBW GENMASK(31, 30)
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#define B_RX_BT_SG0 GENMASK(25, 22)
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@ -9040,6 +9073,10 @@
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#define B_DACKN0_V GENMASK(21, 14)
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#define R_DACKN1_CTL 0xC224
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#define B_DACKN1_V GENMASK(21, 14)
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#define R_GAIN_MAP0 0xE44C
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#define B_GAIN_MAP0_EN BIT(0)
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#define R_GAIN_MAP1 0xE54C
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#define B_GAIN_MAP1_EN BIT(0)
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#define R_GOTX_IQKDPK_C0 0xE464
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#define R_GOTX_IQKDPK_C1 0xE564
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#define B_GOTX_IQKDPK GENMASK(28, 27)
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@ -11,6 +11,7 @@
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#include "reg.h"
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#include "rtw8922a.h"
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#include "rtw8922a_rfk.h"
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#include "util.h"
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#define RTW8922A_FW_FORMAT_MAX 0
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#define RTW8922A_FW_BASENAME "rtw89/rtw8922a_fw"
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@ -862,6 +863,37 @@ static void rtw8922a_set_channel_mac(struct rtw89_dev *rtwdev,
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}
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}
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static const u32 rtw8922a_sco_barker_threshold[14] = {
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0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
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0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
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};
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static const u32 rtw8922a_sco_cck_threshold[14] = {
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0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
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0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
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};
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static int rtw8922a_ctrl_sco_cck(struct rtw89_dev *rtwdev,
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u8 primary_ch, enum rtw89_bandwidth bw,
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enum rtw89_phy_idx phy_idx)
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{
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u8 ch_element;
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if (primary_ch >= 14)
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return -EINVAL;
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ch_element = primary_ch - 1;
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rtw89_phy_write32_idx(rtwdev, R_BK_FC0INV, B_BK_FC0INV,
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rtw8922a_sco_barker_threshold[ch_element],
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phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_CCK_FC0INV, B_CCK_FC0INV,
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rtw8922a_sco_cck_threshold[ch_element],
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phy_idx);
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return 0;
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}
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struct rtw8922a_bb_gain {
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u32 gain_g[BB_PATH_NUM_8922A];
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u32 gain_a[BB_PATH_NUM_8922A];
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@ -1022,12 +1054,341 @@ static void rtw8922a_set_gain(struct rtw89_dev *rtwdev,
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rtw8922a_set_rpl_gain(rtwdev, chan, path, phy_idx);
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}
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static void rtw8922a_set_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_rf_path path)
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{
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struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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s8 value = -gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; /* S(8,2) */
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u8 fraction = value & 0x3;
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if (fraction) {
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rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20,
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(0x4 - fraction) << 1);
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rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40,
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(0x4 - fraction) << 1);
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value >>= 2;
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rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
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value + 1 + 0xdc);
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} else {
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rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0);
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rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0);
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value >>= 2;
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rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
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value + 0xdc);
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}
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}
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static void rtw8922a_set_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_rf_path path)
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{
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static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8};
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static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608};
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static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8};
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static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8};
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static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8};
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struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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enum rtw89_gain_offset gain_band;
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s8 v1, v2, v3;
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s32 value;
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gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
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value = gain->offset[path][gain_band];
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rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8);
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value *= -4;
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v1 = clamp_t(s32, value, S8_MIN, S8_MAX);
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value -= v1;
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v2 = clamp_t(s32, value, S8_MIN, S8_MAX);
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value -= v2;
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v3 = clamp_t(s32, value, S8_MIN, S8_MAX);
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rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1);
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rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2);
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rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3);
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rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1);
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rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2);
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rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3);
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}
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static void rtw8922a_set_rx_gain_normal(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_rf_path path)
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{
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struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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if (!gain->offset_valid)
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return;
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if (chan->band_type == RTW89_BAND_2G)
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rtw8922a_set_rx_gain_normal_cck(rtwdev, chan, path);
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rtw8922a_set_rx_gain_normal_ofdm(rtwdev, chan, path);
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}
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static void rtw8922a_set_cck_parameters(struct rtw89_dev *rtwdev, u8 central_ch,
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enum rtw89_phy_idx phy_idx)
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{
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if (central_ch == 14) {
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx);
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} else {
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx);
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}
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}
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static void rtw8922a_ctrl_ch(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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static const u32 band_sel[2] = {0x4160, 0x4560};
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u16 central_freq = chan->freq;
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u8 central_ch = chan->channel;
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u8 band = chan->band_type;
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bool is_2g = band == RTW89_BAND_2G;
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u8 chan_idx;
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u8 path;
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u8 sco;
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if (!central_freq) {
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rtw89_warn(rtwdev, "Invalid central_freq\n");
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return;
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}
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rtw8922a_set_gain(rtwdev, chan, RF_PATH_A, phy_idx);
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rtw8922a_set_gain(rtwdev, chan, RF_PATH_B, phy_idx);
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for (path = RF_PATH_A; path < BB_PATH_NUM_8922A; path++)
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rtw89_phy_write32_idx(rtwdev, band_sel[path], BIT((26)), is_2g, phy_idx);
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rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_A);
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rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_B);
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rtw89_phy_write32_idx(rtwdev, R_FC0, B_FC0, central_freq, phy_idx);
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sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_FC0_INV, sco, phy_idx);
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if (band == RTW89_BAND_2G)
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rtw8922a_set_cck_parameters(rtwdev, central_ch, phy_idx);
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chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
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rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
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}
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static void
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rtw8922a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_sb, u8 bw,
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enum rtw89_phy_idx phy_idx)
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{
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switch (bw) {
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case RTW89_CHANNEL_WIDTH_5:
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
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break;
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case RTW89_CHANNEL_WIDTH_10:
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
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break;
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case RTW89_CHANNEL_WIDTH_20:
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
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break;
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case RTW89_CHANNEL_WIDTH_40:
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
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break;
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case RTW89_CHANNEL_WIDTH_80:
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
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||||
break;
|
||||
case RTW89_CHANNEL_WIDTH_160:
|
||||
rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
|
||||
break;
|
||||
default:
|
||||
rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri_sb:%d)\n", bw,
|
||||
pri_sb);
|
||||
break;
|
||||
}
|
||||
|
||||
if (bw == RTW89_CHANNEL_WIDTH_40)
|
||||
rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 1, phy_idx);
|
||||
else
|
||||
rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx);
|
||||
}
|
||||
|
||||
static u32 rtw8922a_spur_freq(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
|
||||
#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
|
||||
#define MAX_TONE_NUM 2048
|
||||
|
||||
static void rtw8922a_set_csi_tone_idx(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan,
|
||||
enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
s32 freq_diff, csi_idx, csi_tone_idx;
|
||||
u32 spur_freq;
|
||||
|
||||
spur_freq = rtw8922a_spur_freq(rtwdev, chan);
|
||||
if (spur_freq == 0) {
|
||||
rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN,
|
||||
0, phy_idx);
|
||||
return;
|
||||
}
|
||||
|
||||
freq_diff = (spur_freq - chan->freq) * 1000000;
|
||||
csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
|
||||
s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
|
||||
|
||||
rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_TONE_IDX,
|
||||
csi_tone_idx, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN, 1, phy_idx);
|
||||
}
|
||||
|
||||
static const struct rtw89_nbi_reg_def rtw8922a_nbi_reg_def[] = {
|
||||
[RF_PATH_A] = {
|
||||
.notch1_idx = {0x41a0, 0xFF},
|
||||
.notch1_frac_idx = {0x41a0, 0xC00},
|
||||
.notch1_en = {0x41a0, 0x1000},
|
||||
.notch2_idx = {0x41ac, 0xFF},
|
||||
.notch2_frac_idx = {0x41ac, 0xC00},
|
||||
.notch2_en = {0x41ac, 0x1000},
|
||||
},
|
||||
[RF_PATH_B] = {
|
||||
.notch1_idx = {0x45a0, 0xFF},
|
||||
.notch1_frac_idx = {0x45a0, 0xC00},
|
||||
.notch1_en = {0x45a0, 0x1000},
|
||||
.notch2_idx = {0x45ac, 0xFF},
|
||||
.notch2_frac_idx = {0x45ac, 0xC00},
|
||||
.notch2_en = {0x45ac, 0x1000},
|
||||
},
|
||||
};
|
||||
|
||||
static void rtw8922a_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan,
|
||||
enum rtw89_rf_path path,
|
||||
enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
const struct rtw89_nbi_reg_def *nbi = &rtw8922a_nbi_reg_def[path];
|
||||
s32 nbi_frac_idx, nbi_frac_tone_idx;
|
||||
s32 nbi_idx, nbi_tone_idx;
|
||||
bool notch2_chk = false;
|
||||
u32 spur_freq, fc;
|
||||
s32 freq_diff;
|
||||
|
||||
spur_freq = rtw8922a_spur_freq(rtwdev, chan);
|
||||
if (spur_freq == 0) {
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
|
||||
nbi->notch1_en.mask, 0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
|
||||
nbi->notch2_en.mask, 0, phy_idx);
|
||||
return;
|
||||
}
|
||||
|
||||
fc = chan->freq;
|
||||
if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
|
||||
fc = (spur_freq > fc) ? fc + 40 : fc - 40;
|
||||
if ((fc > spur_freq &&
|
||||
chan->channel < chan->primary_channel) ||
|
||||
(fc < spur_freq &&
|
||||
chan->channel > chan->primary_channel))
|
||||
notch2_chk = true;
|
||||
}
|
||||
|
||||
freq_diff = (spur_freq - fc) * 1000000;
|
||||
nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
|
||||
&nbi_frac_idx);
|
||||
|
||||
if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
|
||||
s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
|
||||
} else {
|
||||
u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
|
||||
128 : 256;
|
||||
|
||||
s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
|
||||
}
|
||||
nbi_frac_tone_idx =
|
||||
s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
|
||||
|
||||
if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_idx.addr,
|
||||
nbi->notch2_idx.mask, nbi_tone_idx, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_frac_idx.addr,
|
||||
nbi->notch2_frac_idx.mask, nbi_frac_tone_idx,
|
||||
phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
|
||||
nbi->notch2_en.mask, 0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
|
||||
nbi->notch2_en.mask, 1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
|
||||
nbi->notch1_en.mask, 0, phy_idx);
|
||||
} else {
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_idx.addr,
|
||||
nbi->notch1_idx.mask, nbi_tone_idx, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_frac_idx.addr,
|
||||
nbi->notch1_frac_idx.mask, nbi_frac_tone_idx,
|
||||
phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
|
||||
nbi->notch1_en.mask, 0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
|
||||
nbi->notch1_en.mask, 1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
|
||||
nbi->notch2_en.mask, 0, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
static void rtw8922a_spur_elimination(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan,
|
||||
enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
rtw8922a_set_csi_tone_idx(rtwdev, chan, phy_idx);
|
||||
rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A, phy_idx);
|
||||
rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B, phy_idx);
|
||||
}
|
||||
|
||||
static void rtw8922a_ctrl_afe_dac(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
|
||||
@ -1377,11 +1738,40 @@ static void rtw8922a_bb_sethw(struct rtw89_dev *rtwdev)
|
||||
rtw8922a_ctrl_mlo(rtwdev, rtwdev->mlo_dbcc_mode);
|
||||
}
|
||||
|
||||
static void rtw8922a_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en,
|
||||
enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
if (cck_en) {
|
||||
rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
|
||||
0, phy_idx);
|
||||
} else {
|
||||
rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 1, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx);
|
||||
rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
|
||||
1, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
static void rtw8922a_set_channel_bb(struct rtw89_dev *rtwdev,
|
||||
const struct rtw89_chan *chan,
|
||||
enum rtw89_phy_idx phy_idx)
|
||||
{
|
||||
bool cck_en = chan->band_type == RTW89_BAND_2G;
|
||||
u8 pri_sb = chan->pri_sb_idx;
|
||||
|
||||
if (cck_en)
|
||||
rtw8922a_ctrl_sco_cck(rtwdev, chan->primary_channel,
|
||||
chan->band_width, phy_idx);
|
||||
|
||||
rtw8922a_ctrl_ch(rtwdev, chan, phy_idx);
|
||||
rtw8922a_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
|
||||
rtw8922a_ctrl_cck_en(rtwdev, cck_en, phy_idx);
|
||||
rtw8922a_spur_elimination(rtwdev, chan, phy_idx);
|
||||
|
||||
rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
|
||||
rtw8922a_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
|
||||
}
|
||||
|
||||
static void rtw8922a_set_channel(struct rtw89_dev *rtwdev,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user