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ARM: at91: suspend both memory controllers on at91sam9263

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For the past three years, we have had a #warning in
mach-at91 about the sdram_selfrefresh_enable or
at91sam9_standby functions possibly not working on
at91sam9263. In the meantime a function was added
to do the right thing on at91sam9g45, which looks like
it should also work on '9263.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: remove paragraph in commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Arnd Bergmann 2013-01-25 22:44:17 +00:00 committed by Nicolas Ferre
parent 13ab6aeb49
commit f5fa4098c3
3 changed files with 28 additions and 6 deletions
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2
arch/arm/mach-at91/cpuidle.c
View File

@ -38,6 +38,8 @@ static int at91_enter_idle(struct cpuidle_device *dev,
at91rm9200_standby(); at91rm9200_standby();
else if (cpu_is_at91sam9g45()) else if (cpu_is_at91sam9g45())
at91sam9g45_standby(); at91sam9g45_standby();
else if (cpu_is_at91sam9263())
at91sam9263_standby();
else else
at91sam9_standby(); at91sam9_standby();

2
arch/arm/mach-at91/pm.c
View File

@ -267,6 +267,8 @@ static int at91_pm_enter(suspend_state_t state)
at91rm9200_standby(); at91rm9200_standby();
else if (cpu_is_at91sam9g45()) else if (cpu_is_at91sam9g45())
at91sam9g45_standby(); at91sam9g45_standby();
else if (cpu_is_at91sam9263())
at91sam9263_standby();
else else
at91sam9_standby(); at91sam9_standby();
break; break;

30
arch/arm/mach-at91/pm.h
View File

@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void)
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
} }
#ifdef CONFIG_SOC_AT91SAM9263 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
/* * remember.
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
* handle those cases both here and in the Suspend-To-RAM support.
*/ */
#warning Assuming EB1 SDRAM controller is *NOT* used static inline void at91sam9263_standby(void)
#endif {
u32 lpr0, lpr1;
u32 saved_lpr0, saved_lpr1;
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
/* self-refresh mode now */
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}
static inline void at91sam9_standby(void) static inline void at91sam9_standby(void)
{ {