media: intel/ipu6: input system ABI between firmware and driver
Implement the input system firmware ABIs in the ISYS driver, including stream configuration, control command, capture request and response. Signed-off-by: Bingbu Cao <bingbu.cao@intel.com> Co-developed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
Bingbu Cao
Hans Verkuil
parent
b71f777d89
commit
f625e8d7ff
487
drivers/media/pci/intel/ipu6/ipu6-fw-isys.c
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487
drivers/media/pci/intel/ipu6/ipu6-fw-isys.c
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@ -0,0 +1,487 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013--2024 Intel Corporation
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*/
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#include <linux/cacheflush.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "ipu6-bus.h"
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#include "ipu6-fw-com.h"
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#include "ipu6-isys.h"
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#include "ipu6-platform-isys-csi2-reg.h"
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#include "ipu6-platform-regs.h"
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static const char send_msg_types[N_IPU6_FW_ISYS_SEND_TYPE][32] = {
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"STREAM_OPEN",
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"STREAM_START",
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"STREAM_START_AND_CAPTURE",
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"STREAM_CAPTURE",
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"STREAM_STOP",
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"STREAM_FLUSH",
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"STREAM_CLOSE"
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};
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static int handle_proxy_response(struct ipu6_isys *isys, unsigned int req_id)
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{
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struct device *dev = &isys->adev->auxdev.dev;
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struct ipu6_fw_isys_proxy_resp_info_abi *resp;
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int ret;
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resp = ipu6_recv_get_token(isys->fwcom, IPU6_BASE_PROXY_RECV_QUEUES);
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if (!resp)
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return 1;
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dev_dbg(dev, "Proxy response: id %u, error %u, details %u\n",
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resp->request_id, resp->error_info.error,
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resp->error_info.error_details);
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ret = req_id == resp->request_id ? 0 : -EIO;
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ipu6_recv_put_token(isys->fwcom, IPU6_BASE_PROXY_RECV_QUEUES);
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return ret;
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}
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int ipu6_fw_isys_send_proxy_token(struct ipu6_isys *isys,
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unsigned int req_id,
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unsigned int index,
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unsigned int offset, u32 value)
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{
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struct ipu6_fw_com_context *ctx = isys->fwcom;
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struct device *dev = &isys->adev->auxdev.dev;
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struct ipu6_fw_proxy_send_queue_token *token;
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unsigned int timeout = 1000;
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int ret;
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dev_dbg(dev,
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"proxy send: req_id 0x%x, index %d, offset 0x%x, value 0x%x\n",
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req_id, index, offset, value);
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token = ipu6_send_get_token(ctx, IPU6_BASE_PROXY_SEND_QUEUES);
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if (!token)
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return -EBUSY;
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token->request_id = req_id;
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token->region_index = index;
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token->offset = offset;
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token->value = value;
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ipu6_send_put_token(ctx, IPU6_BASE_PROXY_SEND_QUEUES);
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do {
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usleep_range(100, 110);
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ret = handle_proxy_response(isys, req_id);
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if (!ret)
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break;
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if (ret == -EIO) {
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dev_err(dev, "Proxy respond with unexpected id\n");
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break;
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}
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timeout--;
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} while (ret && timeout);
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if (!timeout)
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dev_err(dev, "Proxy response timed out\n");
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return ret;
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}
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int ipu6_fw_isys_complex_cmd(struct ipu6_isys *isys,
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const unsigned int stream_handle,
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void *cpu_mapped_buf,
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dma_addr_t dma_mapped_buf,
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size_t size, u16 send_type)
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{
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struct ipu6_fw_com_context *ctx = isys->fwcom;
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struct device *dev = &isys->adev->auxdev.dev;
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struct ipu6_fw_send_queue_token *token;
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if (send_type >= N_IPU6_FW_ISYS_SEND_TYPE)
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return -EINVAL;
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dev_dbg(dev, "send_token: %s\n", send_msg_types[send_type]);
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/*
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* Time to flush cache in case we have some payload. Not all messages
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* have that
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*/
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if (cpu_mapped_buf)
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clflush_cache_range(cpu_mapped_buf, size);
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token = ipu6_send_get_token(ctx,
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stream_handle + IPU6_BASE_MSG_SEND_QUEUES);
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if (!token)
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return -EBUSY;
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token->payload = dma_mapped_buf;
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token->buf_handle = (unsigned long)cpu_mapped_buf;
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token->send_type = send_type;
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ipu6_send_put_token(ctx, stream_handle + IPU6_BASE_MSG_SEND_QUEUES);
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return 0;
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}
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int ipu6_fw_isys_simple_cmd(struct ipu6_isys *isys,
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const unsigned int stream_handle, u16 send_type)
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{
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return ipu6_fw_isys_complex_cmd(isys, stream_handle, NULL, 0, 0,
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send_type);
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}
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int ipu6_fw_isys_close(struct ipu6_isys *isys)
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{
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struct device *dev = &isys->adev->auxdev.dev;
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int retry = IPU6_ISYS_CLOSE_RETRY;
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unsigned long flags;
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void *fwcom;
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int ret;
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/*
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* Stop the isys fw. Actual close takes
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* some time as the FW must stop its actions including code fetch
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* to SP icache.
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* spinlock to wait the interrupt handler to be finished
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*/
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spin_lock_irqsave(&isys->power_lock, flags);
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ret = ipu6_fw_com_close(isys->fwcom);
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fwcom = isys->fwcom;
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isys->fwcom = NULL;
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spin_unlock_irqrestore(&isys->power_lock, flags);
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if (ret)
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dev_err(dev, "Device close failure: %d\n", ret);
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/* release probably fails if the close failed. Let's try still */
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do {
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usleep_range(400, 500);
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ret = ipu6_fw_com_release(fwcom, 0);
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retry--;
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} while (ret && retry);
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if (ret) {
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dev_err(dev, "Device release time out %d\n", ret);
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spin_lock_irqsave(&isys->power_lock, flags);
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isys->fwcom = fwcom;
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spin_unlock_irqrestore(&isys->power_lock, flags);
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}
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return ret;
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}
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void ipu6_fw_isys_cleanup(struct ipu6_isys *isys)
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{
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int ret;
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ret = ipu6_fw_com_release(isys->fwcom, 1);
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if (ret < 0)
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dev_warn(&isys->adev->auxdev.dev,
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"Device busy, fw_com release failed.");
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isys->fwcom = NULL;
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}
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static void start_sp(struct ipu6_bus_device *adev)
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{
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struct ipu6_isys *isys = ipu6_bus_get_drvdata(adev);
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void __iomem *spc_regs_base = isys->pdata->base +
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isys->pdata->ipdata->hw_variant.spc_offset;
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u32 val = IPU6_ISYS_SPC_STATUS_START |
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IPU6_ISYS_SPC_STATUS_RUN |
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IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE;
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val |= isys->icache_prefetch ? IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH : 0;
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writel(val, spc_regs_base + IPU6_ISYS_REG_SPC_STATUS_CTRL);
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}
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static int query_sp(struct ipu6_bus_device *adev)
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{
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struct ipu6_isys *isys = ipu6_bus_get_drvdata(adev);
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void __iomem *spc_regs_base = isys->pdata->base +
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isys->pdata->ipdata->hw_variant.spc_offset;
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u32 val;
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val = readl(spc_regs_base + IPU6_ISYS_REG_SPC_STATUS_CTRL);
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/* return true when READY == 1, START == 0 */
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val &= IPU6_ISYS_SPC_STATUS_READY | IPU6_ISYS_SPC_STATUS_START;
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return val == IPU6_ISYS_SPC_STATUS_READY;
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}
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static int ipu6_isys_fwcom_cfg_init(struct ipu6_isys *isys,
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struct ipu6_fw_com_cfg *fwcom,
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unsigned int num_streams)
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{
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unsigned int max_send_queues, max_sram_blocks, max_devq_size;
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struct ipu6_fw_syscom_queue_config *input_queue_cfg;
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struct ipu6_fw_syscom_queue_config *output_queue_cfg;
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struct device *dev = &isys->adev->auxdev.dev;
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int type_proxy = IPU6_FW_ISYS_QUEUE_TYPE_PROXY;
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int type_dev = IPU6_FW_ISYS_QUEUE_TYPE_DEV;
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int type_msg = IPU6_FW_ISYS_QUEUE_TYPE_MSG;
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int base_dev_send = IPU6_BASE_DEV_SEND_QUEUES;
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int base_msg_send = IPU6_BASE_MSG_SEND_QUEUES;
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int base_msg_recv = IPU6_BASE_MSG_RECV_QUEUES;
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struct ipu6_fw_isys_fw_config *isys_fw_cfg;
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u32 num_in_message_queues;
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unsigned int max_streams;
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unsigned int size;
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unsigned int i;
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max_streams = isys->pdata->ipdata->max_streams;
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max_send_queues = isys->pdata->ipdata->max_send_queues;
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max_sram_blocks = isys->pdata->ipdata->max_sram_blocks;
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max_devq_size = isys->pdata->ipdata->max_devq_size;
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num_in_message_queues = clamp(num_streams, 1U, max_streams);
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isys_fw_cfg = devm_kzalloc(dev, sizeof(*isys_fw_cfg), GFP_KERNEL);
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if (!isys_fw_cfg)
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return -ENOMEM;
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isys_fw_cfg->num_send_queues[type_proxy] = IPU6_N_MAX_PROXY_SEND_QUEUES;
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isys_fw_cfg->num_send_queues[type_dev] = IPU6_N_MAX_DEV_SEND_QUEUES;
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isys_fw_cfg->num_send_queues[type_msg] = num_in_message_queues;
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isys_fw_cfg->num_recv_queues[type_proxy] = IPU6_N_MAX_PROXY_RECV_QUEUES;
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/* Common msg/dev return queue */
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isys_fw_cfg->num_recv_queues[type_dev] = 0;
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isys_fw_cfg->num_recv_queues[type_msg] = 1;
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size = sizeof(*input_queue_cfg) * max_send_queues;
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input_queue_cfg = devm_kzalloc(dev, size, GFP_KERNEL);
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if (!input_queue_cfg)
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return -ENOMEM;
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size = sizeof(*output_queue_cfg) * IPU6_N_MAX_RECV_QUEUES;
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output_queue_cfg = devm_kzalloc(dev, size, GFP_KERNEL);
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if (!output_queue_cfg)
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return -ENOMEM;
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fwcom->input = input_queue_cfg;
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fwcom->output = output_queue_cfg;
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fwcom->num_input_queues = isys_fw_cfg->num_send_queues[type_proxy] +
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isys_fw_cfg->num_send_queues[type_dev] +
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isys_fw_cfg->num_send_queues[type_msg];
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fwcom->num_output_queues = isys_fw_cfg->num_recv_queues[type_proxy] +
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isys_fw_cfg->num_recv_queues[type_dev] +
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isys_fw_cfg->num_recv_queues[type_msg];
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/* SRAM partitioning. Equal partitioning is set. */
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for (i = 0; i < max_sram_blocks; i++) {
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if (i < num_in_message_queues)
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isys_fw_cfg->buffer_partition.num_gda_pages[i] =
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(IPU6_DEVICE_GDA_NR_PAGES *
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IPU6_DEVICE_GDA_VIRT_FACTOR) /
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num_in_message_queues;
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else
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isys_fw_cfg->buffer_partition.num_gda_pages[i] = 0;
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}
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/* FW assumes proxy interface at fwcom queue 0 */
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for (i = 0; i < isys_fw_cfg->num_send_queues[type_proxy]; i++) {
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input_queue_cfg[i].token_size =
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sizeof(struct ipu6_fw_proxy_send_queue_token);
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input_queue_cfg[i].queue_size = IPU6_ISYS_SIZE_PROXY_SEND_QUEUE;
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}
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for (i = 0; i < isys_fw_cfg->num_send_queues[type_dev]; i++) {
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input_queue_cfg[base_dev_send + i].token_size =
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sizeof(struct ipu6_fw_send_queue_token);
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input_queue_cfg[base_dev_send + i].queue_size = max_devq_size;
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}
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for (i = 0; i < isys_fw_cfg->num_send_queues[type_msg]; i++) {
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input_queue_cfg[base_msg_send + i].token_size =
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sizeof(struct ipu6_fw_send_queue_token);
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input_queue_cfg[base_msg_send + i].queue_size =
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IPU6_ISYS_SIZE_SEND_QUEUE;
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}
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for (i = 0; i < isys_fw_cfg->num_recv_queues[type_proxy]; i++) {
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output_queue_cfg[i].token_size =
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sizeof(struct ipu6_fw_proxy_resp_queue_token);
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output_queue_cfg[i].queue_size =
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IPU6_ISYS_SIZE_PROXY_RECV_QUEUE;
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}
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/* There is no recv DEV queue */
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for (i = 0; i < isys_fw_cfg->num_recv_queues[type_msg]; i++) {
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output_queue_cfg[base_msg_recv + i].token_size =
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sizeof(struct ipu6_fw_resp_queue_token);
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output_queue_cfg[base_msg_recv + i].queue_size =
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IPU6_ISYS_SIZE_RECV_QUEUE;
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}
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fwcom->dmem_addr = isys->pdata->ipdata->hw_variant.dmem_offset;
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fwcom->specific_addr = isys_fw_cfg;
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fwcom->specific_size = sizeof(*isys_fw_cfg);
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return 0;
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}
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int ipu6_fw_isys_init(struct ipu6_isys *isys, unsigned int num_streams)
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{
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struct device *dev = &isys->adev->auxdev.dev;
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int retry = IPU6_ISYS_OPEN_RETRY;
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struct ipu6_fw_com_cfg fwcom = {
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.cell_start = start_sp,
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.cell_ready = query_sp,
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.buttress_boot_offset = SYSCOM_BUTTRESS_FW_PARAMS_ISYS_OFFSET,
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};
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int ret;
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ipu6_isys_fwcom_cfg_init(isys, &fwcom, num_streams);
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isys->fwcom = ipu6_fw_com_prepare(&fwcom, isys->adev,
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isys->pdata->base);
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if (!isys->fwcom) {
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dev_err(dev, "isys fw com prepare failed\n");
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return -EIO;
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}
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ret = ipu6_fw_com_open(isys->fwcom);
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if (ret) {
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dev_err(dev, "isys fw com open failed %d\n", ret);
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return ret;
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}
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do {
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usleep_range(400, 500);
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if (ipu6_fw_com_ready(isys->fwcom))
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break;
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retry--;
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} while (retry > 0);
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if (!retry) {
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dev_err(dev, "isys port open ready failed %d\n", ret);
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ipu6_fw_isys_close(isys);
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ret = -EIO;
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}
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return ret;
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}
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struct ipu6_fw_isys_resp_info_abi *
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ipu6_fw_isys_get_resp(void *context, unsigned int queue)
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{
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return ipu6_recv_get_token(context, queue);
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}
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void ipu6_fw_isys_put_resp(void *context, unsigned int queue)
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{
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ipu6_recv_put_token(context, queue);
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}
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void ipu6_fw_isys_dump_stream_cfg(struct device *dev,
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struct ipu6_fw_isys_stream_cfg_data_abi *cfg)
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{
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unsigned int i;
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dev_dbg(dev, "-----------------------------------------------------\n");
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dev_dbg(dev, "IPU6_FW_ISYS_STREAM_CFG_DATA\n");
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dev_dbg(dev, "compfmt = %d\n", cfg->vc);
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dev_dbg(dev, "src = %d\n", cfg->src);
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dev_dbg(dev, "vc = %d\n", cfg->vc);
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dev_dbg(dev, "isl_use = %d\n", cfg->isl_use);
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dev_dbg(dev, "sensor_type = %d\n", cfg->sensor_type);
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dev_dbg(dev, "send_irq_sof_discarded = %d\n",
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cfg->send_irq_sof_discarded);
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dev_dbg(dev, "send_irq_eof_discarded = %d\n",
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cfg->send_irq_eof_discarded);
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dev_dbg(dev, "send_resp_sof_discarded = %d\n",
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cfg->send_resp_sof_discarded);
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dev_dbg(dev, "send_resp_eof_discarded = %d\n",
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cfg->send_resp_eof_discarded);
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dev_dbg(dev, "crop:\n");
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dev_dbg(dev, "\t.left_top = [%d, %d]\n", cfg->crop.left_offset,
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cfg->crop.top_offset);
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dev_dbg(dev, "\t.right_bottom = [%d, %d]\n", cfg->crop.right_offset,
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cfg->crop.bottom_offset);
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|
||||
dev_dbg(dev, "nof_input_pins = %d\n", cfg->nof_input_pins);
|
||||
for (i = 0; i < cfg->nof_input_pins; i++) {
|
||||
dev_dbg(dev, "input pin[%d]:\n", i);
|
||||
dev_dbg(dev, "\t.dt = 0x%0x\n", cfg->input_pins[i].dt);
|
||||
dev_dbg(dev, "\t.mipi_store_mode = %d\n",
|
||||
cfg->input_pins[i].mipi_store_mode);
|
||||
dev_dbg(dev, "\t.bits_per_pix = %d\n",
|
||||
cfg->input_pins[i].bits_per_pix);
|
||||
dev_dbg(dev, "\t.mapped_dt = 0x%0x\n",
|
||||
cfg->input_pins[i].mapped_dt);
|
||||
dev_dbg(dev, "\t.input_res = %dx%d\n",
|
||||
cfg->input_pins[i].input_res.width,
|
||||
cfg->input_pins[i].input_res.height);
|
||||
dev_dbg(dev, "\t.mipi_decompression = %d\n",
|
||||
cfg->input_pins[i].mipi_decompression);
|
||||
dev_dbg(dev, "\t.capture_mode = %d\n",
|
||||
cfg->input_pins[i].capture_mode);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "nof_output_pins = %d\n", cfg->nof_output_pins);
|
||||
for (i = 0; i < cfg->nof_output_pins; i++) {
|
||||
dev_dbg(dev, "output_pin[%d]:\n", i);
|
||||
dev_dbg(dev, "\t.input_pin_id = %d\n",
|
||||
cfg->output_pins[i].input_pin_id);
|
||||
dev_dbg(dev, "\t.output_res = %dx%d\n",
|
||||
cfg->output_pins[i].output_res.width,
|
||||
cfg->output_pins[i].output_res.height);
|
||||
dev_dbg(dev, "\t.stride = %d\n", cfg->output_pins[i].stride);
|
||||
dev_dbg(dev, "\t.pt = %d\n", cfg->output_pins[i].pt);
|
||||
dev_dbg(dev, "\t.payload_buf_size = %d\n",
|
||||
cfg->output_pins[i].payload_buf_size);
|
||||
dev_dbg(dev, "\t.ft = %d\n", cfg->output_pins[i].ft);
|
||||
dev_dbg(dev, "\t.watermark_in_lines = %d\n",
|
||||
cfg->output_pins[i].watermark_in_lines);
|
||||
dev_dbg(dev, "\t.send_irq = %d\n",
|
||||
cfg->output_pins[i].send_irq);
|
||||
dev_dbg(dev, "\t.reserve_compression = %d\n",
|
||||
cfg->output_pins[i].reserve_compression);
|
||||
dev_dbg(dev, "\t.snoopable = %d\n",
|
||||
cfg->output_pins[i].snoopable);
|
||||
dev_dbg(dev, "\t.error_handling_enable = %d\n",
|
||||
cfg->output_pins[i].error_handling_enable);
|
||||
dev_dbg(dev, "\t.sensor_type = %d\n",
|
||||
cfg->output_pins[i].sensor_type);
|
||||
}
|
||||
dev_dbg(dev, "-----------------------------------------------------\n");
|
||||
}
|
||||
|
||||
void
|
||||
ipu6_fw_isys_dump_frame_buff_set(struct device *dev,
|
||||
struct ipu6_fw_isys_frame_buff_set_abi *buf,
|
||||
unsigned int outputs)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
dev_dbg(dev, "-----------------------------------------------------\n");
|
||||
dev_dbg(dev, "IPU6_FW_ISYS_FRAME_BUFF_SET\n");
|
||||
|
||||
for (i = 0; i < outputs; i++) {
|
||||
dev_dbg(dev, "output_pin[%d]:\n", i);
|
||||
dev_dbg(dev, "\t.out_buf_id = %llu\n",
|
||||
buf->output_pins[i].out_buf_id);
|
||||
dev_dbg(dev, "\t.addr = 0x%x\n", buf->output_pins[i].addr);
|
||||
dev_dbg(dev, "\t.compress = %d\n",
|
||||
buf->output_pins[i].compress);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "send_irq_sof = 0x%x\n", buf->send_irq_sof);
|
||||
dev_dbg(dev, "send_irq_eof = 0x%x\n", buf->send_irq_eof);
|
||||
dev_dbg(dev, "send_resp_sof = 0x%x\n", buf->send_resp_sof);
|
||||
dev_dbg(dev, "send_resp_eof = 0x%x\n", buf->send_resp_eof);
|
||||
dev_dbg(dev, "send_irq_capture_ack = 0x%x\n",
|
||||
buf->send_irq_capture_ack);
|
||||
dev_dbg(dev, "send_irq_capture_done = 0x%x\n",
|
||||
buf->send_irq_capture_done);
|
||||
dev_dbg(dev, "send_resp_capture_ack = 0x%x\n",
|
||||
buf->send_resp_capture_ack);
|
||||
dev_dbg(dev, "send_resp_capture_done = 0x%x\n",
|
||||
buf->send_resp_capture_done);
|
||||
|
||||
dev_dbg(dev, "-----------------------------------------------------\n");
|
||||
}
|
||||
596
drivers/media/pci/intel/ipu6/ipu6-fw-isys.h
Normal file
596
drivers/media/pci/intel/ipu6/ipu6-fw-isys.h
Normal file
@ -0,0 +1,596 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (C) 2013--2024 Intel Corporation */
|
||||
|
||||
#ifndef IPU6_FW_ISYS_H
|
||||
#define IPU6_FW_ISYS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device;
|
||||
struct ipu6_isys;
|
||||
|
||||
/* Max number of Input/Output Pins */
|
||||
#define IPU6_MAX_IPINS 4
|
||||
|
||||
#define IPU6_MAX_OPINS ((IPU6_MAX_IPINS) + 1)
|
||||
|
||||
#define IPU6_STREAM_ID_MAX 16
|
||||
#define IPU6_NONSECURE_STREAM_ID_MAX 12
|
||||
#define IPU6_DEV_SEND_QUEUE_SIZE (IPU6_STREAM_ID_MAX)
|
||||
#define IPU6_NOF_SRAM_BLOCKS_MAX (IPU6_STREAM_ID_MAX)
|
||||
#define IPU6_N_MAX_MSG_SEND_QUEUES (IPU6_STREAM_ID_MAX)
|
||||
#define IPU6SE_STREAM_ID_MAX 8
|
||||
#define IPU6SE_NONSECURE_STREAM_ID_MAX 4
|
||||
#define IPU6SE_DEV_SEND_QUEUE_SIZE (IPU6SE_STREAM_ID_MAX)
|
||||
#define IPU6SE_NOF_SRAM_BLOCKS_MAX (IPU6SE_STREAM_ID_MAX)
|
||||
#define IPU6SE_N_MAX_MSG_SEND_QUEUES (IPU6SE_STREAM_ID_MAX)
|
||||
|
||||
/* Single return queue for all streams/commands type */
|
||||
#define IPU6_N_MAX_MSG_RECV_QUEUES 1
|
||||
/* Single device queue for high priority commands (bypass in-order queue) */
|
||||
#define IPU6_N_MAX_DEV_SEND_QUEUES 1
|
||||
/* Single dedicated send queue for proxy interface */
|
||||
#define IPU6_N_MAX_PROXY_SEND_QUEUES 1
|
||||
/* Single dedicated recv queue for proxy interface */
|
||||
#define IPU6_N_MAX_PROXY_RECV_QUEUES 1
|
||||
/* Send queues layout */
|
||||
#define IPU6_BASE_PROXY_SEND_QUEUES 0
|
||||
#define IPU6_BASE_DEV_SEND_QUEUES \
|
||||
(IPU6_BASE_PROXY_SEND_QUEUES + IPU6_N_MAX_PROXY_SEND_QUEUES)
|
||||
#define IPU6_BASE_MSG_SEND_QUEUES \
|
||||
(IPU6_BASE_DEV_SEND_QUEUES + IPU6_N_MAX_DEV_SEND_QUEUES)
|
||||
/* Recv queues layout */
|
||||
#define IPU6_BASE_PROXY_RECV_QUEUES 0
|
||||
#define IPU6_BASE_MSG_RECV_QUEUES \
|
||||
(IPU6_BASE_PROXY_RECV_QUEUES + IPU6_N_MAX_PROXY_RECV_QUEUES)
|
||||
#define IPU6_N_MAX_RECV_QUEUES \
|
||||
(IPU6_BASE_MSG_RECV_QUEUES + IPU6_N_MAX_MSG_RECV_QUEUES)
|
||||
|
||||
#define IPU6_N_MAX_SEND_QUEUES \
|
||||
(IPU6_BASE_MSG_SEND_QUEUES + IPU6_N_MAX_MSG_SEND_QUEUES)
|
||||
#define IPU6SE_N_MAX_SEND_QUEUES \
|
||||
(IPU6_BASE_MSG_SEND_QUEUES + IPU6SE_N_MAX_MSG_SEND_QUEUES)
|
||||
|
||||
/* Max number of planes for frame formats supported by the FW */
|
||||
#define IPU6_PIN_PLANES_MAX 4
|
||||
|
||||
#define IPU6_FW_ISYS_SENSOR_TYPE_START 14
|
||||
#define IPU6_FW_ISYS_SENSOR_TYPE_END 19
|
||||
#define IPU6SE_FW_ISYS_SENSOR_TYPE_START 6
|
||||
#define IPU6SE_FW_ISYS_SENSOR_TYPE_END 11
|
||||
/*
|
||||
* Device close takes some time from last ack message to actual stopping
|
||||
* of the SP processor. As long as the SP processor runs we can't proceed with
|
||||
* clean up of resources.
|
||||
*/
|
||||
#define IPU6_ISYS_OPEN_RETRY 2000
|
||||
#define IPU6_ISYS_CLOSE_RETRY 2000
|
||||
#define IPU6_FW_CALL_TIMEOUT_JIFFIES msecs_to_jiffies(2000)
|
||||
|
||||
enum ipu6_fw_isys_resp_type {
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_OPEN_DONE = 0,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_START_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_STOP_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_FLUSH_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_CLOSE_ACK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_READY,
|
||||
IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_WATERMARK,
|
||||
IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF,
|
||||
IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_DONE,
|
||||
IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_SKIPPED,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_SKIPPED,
|
||||
IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF_DISCARDED,
|
||||
IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF_DISCARDED,
|
||||
IPU6_FW_ISYS_RESP_TYPE_STATS_DATA_READY,
|
||||
N_IPU6_FW_ISYS_RESP_TYPE
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_send_type {
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_OPEN = 0,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_START,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_START_AND_CAPTURE,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_CAPTURE,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_STOP,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_FLUSH,
|
||||
IPU6_FW_ISYS_SEND_TYPE_STREAM_CLOSE,
|
||||
N_IPU6_FW_ISYS_SEND_TYPE
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_queue_type {
|
||||
IPU6_FW_ISYS_QUEUE_TYPE_PROXY = 0,
|
||||
IPU6_FW_ISYS_QUEUE_TYPE_DEV,
|
||||
IPU6_FW_ISYS_QUEUE_TYPE_MSG,
|
||||
N_IPU6_FW_ISYS_QUEUE_TYPE
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_stream_source {
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_0 = 0,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_1,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_2,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_3,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_4,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_5,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_6,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_7,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_8,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_9,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_10,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_11,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_12,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_13,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_14,
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_15,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_2,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_3,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_4,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_5,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_6,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_7,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_8,
|
||||
IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_9,
|
||||
N_IPU6_FW_ISYS_STREAM_SRC
|
||||
};
|
||||
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT0 IPU6_FW_ISYS_STREAM_SRC_PORT_0
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT1 IPU6_FW_ISYS_STREAM_SRC_PORT_1
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT2 IPU6_FW_ISYS_STREAM_SRC_PORT_2
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT3 IPU6_FW_ISYS_STREAM_SRC_PORT_3
|
||||
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTA IPU6_FW_ISYS_STREAM_SRC_PORT_4
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTB IPU6_FW_ISYS_STREAM_SRC_PORT_5
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT0 \
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_6
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT1 \
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_7
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT2 \
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_8
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT3 \
|
||||
IPU6_FW_ISYS_STREAM_SRC_PORT_9
|
||||
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0
|
||||
#define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT1 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1
|
||||
|
||||
/*
|
||||
* enum ipu6_fw_isys_mipi_vc: MIPI csi2 spec
|
||||
* supports up to 4 virtual per physical channel
|
||||
*/
|
||||
enum ipu6_fw_isys_mipi_vc {
|
||||
IPU6_FW_ISYS_MIPI_VC_0 = 0,
|
||||
IPU6_FW_ISYS_MIPI_VC_1,
|
||||
IPU6_FW_ISYS_MIPI_VC_2,
|
||||
IPU6_FW_ISYS_MIPI_VC_3,
|
||||
N_IPU6_FW_ISYS_MIPI_VC
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_frame_format_type {
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV11 = 0, /* 12 bit YUV 411, Y, UV plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */
|
||||
/* 12 bit YUV 420, Intel proprietary tiled format */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV12_TILEY,
|
||||
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */
|
||||
/* Internal format, 2 y lines followed by a uvinterleaved line */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_YUV_LINE,
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RAW8, /* RAW8, 1 plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RAW10, /* RAW10, 1 plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RAW12, /* RAW12, 1 plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RAW14, /* RAW14, 1 plane */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RAW16, /* RAW16, 1 plane */
|
||||
/**
|
||||
* 16 bit RGB, 1 plane. Each 3 sub pixels are packed into one 16 bit
|
||||
* value, 5 bits for R, 6 bits for G and 5 bits for B.
|
||||
*/
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RGB565,
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane, A=Alpha */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */
|
||||
IPU6_FW_ISYS_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. */
|
||||
N_IPU6_FW_ISYS_FRAME_FORMAT
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_pin_type {
|
||||
/* captured as MIPI packets */
|
||||
IPU6_FW_ISYS_PIN_TYPE_MIPI = 0,
|
||||
/* captured through the SoC path */
|
||||
IPU6_FW_ISYS_PIN_TYPE_RAW_SOC = 3,
|
||||
};
|
||||
|
||||
/*
|
||||
* enum ipu6_fw_isys_mipi_store_mode. Describes if long MIPI packets reach
|
||||
* MIPI SRAM with the long packet header or
|
||||
* if not, then only option is to capture it with pin type MIPI.
|
||||
*/
|
||||
enum ipu6_fw_isys_mipi_store_mode {
|
||||
IPU6_FW_ISYS_MIPI_STORE_MODE_NORMAL = 0,
|
||||
IPU6_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER,
|
||||
N_IPU6_FW_ISYS_MIPI_STORE_MODE
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_capture_mode {
|
||||
IPU6_FW_ISYS_CAPTURE_MODE_REGULAR = 0,
|
||||
IPU6_FW_ISYS_CAPTURE_MODE_BURST,
|
||||
N_IPU6_FW_ISYS_CAPTURE_MODE,
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_sensor_mode {
|
||||
IPU6_FW_ISYS_SENSOR_MODE_NORMAL = 0,
|
||||
IPU6_FW_ISYS_SENSOR_MODE_TOBII,
|
||||
N_IPU6_FW_ISYS_SENSOR_MODE,
|
||||
};
|
||||
|
||||
enum ipu6_fw_isys_error {
|
||||
IPU6_FW_ISYS_ERROR_NONE = 0,
|
||||
IPU6_FW_ISYS_ERROR_FW_INTERNAL_CONSISTENCY,
|
||||
IPU6_FW_ISYS_ERROR_HW_CONSISTENCY,
|
||||
IPU6_FW_ISYS_ERROR_DRIVER_INVALID_COMMAND_SEQUENCE,
|
||||
IPU6_FW_ISYS_ERROR_DRIVER_INVALID_DEVICE_CONFIGURATION,
|
||||
IPU6_FW_ISYS_ERROR_DRIVER_INVALID_STREAM_CONFIGURATION,
|
||||
IPU6_FW_ISYS_ERROR_DRIVER_INVALID_FRAME_CONFIGURATION,
|
||||
IPU6_FW_ISYS_ERROR_INSUFFICIENT_RESOURCES,
|
||||
IPU6_FW_ISYS_ERROR_HW_REPORTED_STR2MMIO,
|
||||
IPU6_FW_ISYS_ERROR_HW_REPORTED_SIG2CIO,
|
||||
IPU6_FW_ISYS_ERROR_SENSOR_FW_SYNC,
|
||||
IPU6_FW_ISYS_ERROR_STREAM_IN_SUSPENSION,
|
||||
IPU6_FW_ISYS_ERROR_RESPONSE_QUEUE_FULL,
|
||||
N_IPU6_FW_ISYS_ERROR
|
||||
};
|
||||
|
||||
enum ipu6_fw_proxy_error {
|
||||
IPU6_FW_PROXY_ERROR_NONE = 0,
|
||||
IPU6_FW_PROXY_ERROR_INVALID_WRITE_REGION,
|
||||
IPU6_FW_PROXY_ERROR_INVALID_WRITE_OFFSET,
|
||||
N_IPU6_FW_PROXY_ERROR
|
||||
};
|
||||
|
||||
/* firmware ABI structure below are aligned in firmware, no need pack */
|
||||
struct ipu6_fw_isys_buffer_partition_abi {
|
||||
u32 num_gda_pages[IPU6_STREAM_ID_MAX];
|
||||
};
|
||||
|
||||
struct ipu6_fw_isys_fw_config {
|
||||
struct ipu6_fw_isys_buffer_partition_abi buffer_partition;
|
||||
u32 num_send_queues[N_IPU6_FW_ISYS_QUEUE_TYPE];
|
||||
u32 num_recv_queues[N_IPU6_FW_ISYS_QUEUE_TYPE];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ipu6_fw_isys_resolution_abi: Generic resolution structure.
|
||||
*/
|
||||
struct ipu6_fw_isys_resolution_abi {
|
||||
u32 width;
|
||||
u32 height;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_output_pin_payload_abi - ISYS output pin buffer
|
||||
* @out_buf_id: Points to output pin buffer - buffer identifier
|
||||
* @addr: Points to output pin buffer - CSS Virtual Address
|
||||
* @compress: Request frame compression (1), or not (0)
|
||||
*/
|
||||
struct ipu6_fw_isys_output_pin_payload_abi {
|
||||
u64 out_buf_id;
|
||||
u32 addr;
|
||||
u32 compress;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_output_pin_info_abi - ISYS output pin info
|
||||
* @output_res: output pin resolution
|
||||
* @stride: output stride in Bytes (not valid for statistics)
|
||||
* @watermark_in_lines: pin watermark level in lines
|
||||
* @payload_buf_size: minimum size in Bytes of all buffers that will be
|
||||
* supplied for capture on this pin
|
||||
* @ts_offsets: ts_offsets
|
||||
* @s2m_pixel_soc_pixel_remapping: pixel soc remapping (see the definition of
|
||||
* S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING)
|
||||
* @csi_be_soc_pixel_remapping: see s2m_pixel_soc_pixel_remapping
|
||||
* @send_irq: assert if pin event should trigger irq
|
||||
* @input_pin_id: related input pin id
|
||||
* @pt: pin type -real format "enum ipu6_fw_isys_pin_type"
|
||||
* @ft: frame format type -real format "enum ipu6_fw_isys_frame_format_type"
|
||||
* @reserved: a reserved field
|
||||
* @reserve_compression: reserve compression resources for pin
|
||||
* @snoopable: snoopable
|
||||
* @error_handling_enable: enable error handling
|
||||
* @sensor_type: sensor_type
|
||||
*/
|
||||
struct ipu6_fw_isys_output_pin_info_abi {
|
||||
struct ipu6_fw_isys_resolution_abi output_res;
|
||||
u32 stride;
|
||||
u32 watermark_in_lines;
|
||||
u32 payload_buf_size;
|
||||
u32 ts_offsets[IPU6_PIN_PLANES_MAX];
|
||||
u32 s2m_pixel_soc_pixel_remapping;
|
||||
u32 csi_be_soc_pixel_remapping;
|
||||
u8 send_irq;
|
||||
u8 input_pin_id;
|
||||
u8 pt;
|
||||
u8 ft;
|
||||
u8 reserved;
|
||||
u8 reserve_compression;
|
||||
u8 snoopable;
|
||||
u8 error_handling_enable;
|
||||
u32 sensor_type;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_input_pin_info_abi - ISYS input pin info
|
||||
* @input_res: input resolution
|
||||
* @dt: mipi data type ((enum ipu6_fw_isys_mipi_data_type)
|
||||
* @mipi_store_mode: defines if legacy long packet header will be stored or
|
||||
* discarded if discarded, output pin type for this
|
||||
* input pin can only be MIPI
|
||||
* (enum ipu6_fw_isys_mipi_store_mode)
|
||||
* @bits_per_pix: native bits per pixel
|
||||
* @mapped_dt: actual data type from sensor
|
||||
* @mipi_decompression: defines which compression will be in mipi backend
|
||||
* @crop_first_and_last_lines: Control whether to crop the first and last line
|
||||
* of the input image. Crop done by HW device.
|
||||
* @capture_mode: mode of capture, regular or burst, default value is regular
|
||||
* @reserved: a reserved field
|
||||
*/
|
||||
struct ipu6_fw_isys_input_pin_info_abi {
|
||||
struct ipu6_fw_isys_resolution_abi input_res;
|
||||
u8 dt;
|
||||
u8 mipi_store_mode;
|
||||
u8 bits_per_pix;
|
||||
u8 mapped_dt;
|
||||
u8 mipi_decompression;
|
||||
u8 crop_first_and_last_lines;
|
||||
u8 capture_mode;
|
||||
u8 reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_cropping_abi - ISYS cropping coordinates
|
||||
* @top_offset: Top offset
|
||||
* @left_offset: Left offset
|
||||
* @bottom_offset: Bottom offset
|
||||
* @right_offset: Right offset
|
||||
*/
|
||||
struct ipu6_fw_isys_cropping_abi {
|
||||
s32 top_offset;
|
||||
s32 left_offset;
|
||||
s32 bottom_offset;
|
||||
s32 right_offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_stream_cfg_data_abi - ISYS stream configuration data
|
||||
* ISYS stream configuration data structure
|
||||
* @crop: for extended use and is not used in FW currently
|
||||
* @input_pins: input pin descriptors
|
||||
* @output_pins: output pin descriptors
|
||||
* @compfmt: de-compression setting for User Defined Data
|
||||
* @nof_input_pins: number of input pins
|
||||
* @nof_output_pins: number of output pins
|
||||
* @send_irq_sof_discarded: send irq on discarded frame sof response
|
||||
* - if '1' it will override the send_resp_sof_discarded
|
||||
* and send the response
|
||||
* - if '0' the send_resp_sof_discarded will determine
|
||||
* whether to send the response
|
||||
* @send_irq_eof_discarded: send irq on discarded frame eof response
|
||||
* - if '1' it will override the send_resp_eof_discarded
|
||||
* and send the response
|
||||
* - if '0' the send_resp_eof_discarded will determine
|
||||
* whether to send the response
|
||||
* @send_resp_sof_discarded: send response for discarded frame sof detected,
|
||||
* used only when send_irq_sof_discarded is '0'
|
||||
* @send_resp_eof_discarded: send response for discarded frame eof detected,
|
||||
* used only when send_irq_eof_discarded is '0'
|
||||
* @src: Stream source index e.g. MIPI_generator_0, CSI2-rx_1
|
||||
* @vc: MIPI Virtual Channel (up to 4 virtual per physical channel)
|
||||
* @isl_use: indicates whether stream requires ISL and how
|
||||
* @sensor_type: type of connected sensor, tobii or others, default is 0
|
||||
* @reserved: a reserved field
|
||||
* @reserved2: a reserved field
|
||||
*/
|
||||
struct ipu6_fw_isys_stream_cfg_data_abi {
|
||||
struct ipu6_fw_isys_cropping_abi crop;
|
||||
struct ipu6_fw_isys_input_pin_info_abi input_pins[IPU6_MAX_IPINS];
|
||||
struct ipu6_fw_isys_output_pin_info_abi output_pins[IPU6_MAX_OPINS];
|
||||
u32 compfmt;
|
||||
u8 nof_input_pins;
|
||||
u8 nof_output_pins;
|
||||
u8 send_irq_sof_discarded;
|
||||
u8 send_irq_eof_discarded;
|
||||
u8 send_resp_sof_discarded;
|
||||
u8 send_resp_eof_discarded;
|
||||
u8 src;
|
||||
u8 vc;
|
||||
u8 isl_use;
|
||||
u8 sensor_type;
|
||||
u8 reserved;
|
||||
u8 reserved2;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_frame_buff_set_abi - ISYS frame buffer set (request)
|
||||
* @output_pins: output pin addresses
|
||||
* @send_irq_sof: send irq on frame sof response
|
||||
* - if '1' it will override the send_resp_sof and
|
||||
* send the response
|
||||
* - if '0' the send_resp_sof will determine whether to
|
||||
* send the response
|
||||
* @send_irq_eof: send irq on frame eof response
|
||||
* - if '1' it will override the send_resp_eof and
|
||||
* send the response
|
||||
* - if '0' the send_resp_eof will determine whether to
|
||||
* send the response
|
||||
* @send_irq_capture_ack: send irq on capture ack
|
||||
* @send_irq_capture_done: send irq on capture done
|
||||
* @send_resp_sof: send response for frame sof detected,
|
||||
* used only when send_irq_sof is '0'
|
||||
* @send_resp_eof: send response for frame eof detected,
|
||||
* used only when send_irq_eof is '0'
|
||||
* @send_resp_capture_ack: send response for capture ack event
|
||||
* @send_resp_capture_done: send response for capture done event
|
||||
* @reserved: a reserved field
|
||||
*/
|
||||
struct ipu6_fw_isys_frame_buff_set_abi {
|
||||
struct ipu6_fw_isys_output_pin_payload_abi output_pins[IPU6_MAX_OPINS];
|
||||
u8 send_irq_sof;
|
||||
u8 send_irq_eof;
|
||||
u8 send_irq_capture_ack;
|
||||
u8 send_irq_capture_done;
|
||||
u8 send_resp_sof;
|
||||
u8 send_resp_eof;
|
||||
u8 send_resp_capture_ack;
|
||||
u8 send_resp_capture_done;
|
||||
u8 reserved[8];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_error_info_abi - ISYS error information
|
||||
* @error: error code if something went wrong
|
||||
* @error_details: depending on error code, it may contain additional error info
|
||||
*/
|
||||
struct ipu6_fw_isys_error_info_abi {
|
||||
u32 error;
|
||||
u32 error_details;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_resp_info_abi - ISYS firmware response
|
||||
* @buf_id: buffer ID
|
||||
* @pin: this var is only valid for pin event related responses,
|
||||
* contains pin addresses
|
||||
* @error_info: error information from the FW
|
||||
* @timestamp: Time information for event if available
|
||||
* @stream_handle: stream id the response corresponds to
|
||||
* @type: response type (enum ipu6_fw_isys_resp_type)
|
||||
* @pin_id: pin id that the pin payload corresponds to
|
||||
* @reserved: a reserved field
|
||||
* @reserved2: a reserved field
|
||||
*/
|
||||
struct ipu6_fw_isys_resp_info_abi {
|
||||
u64 buf_id;
|
||||
struct ipu6_fw_isys_output_pin_payload_abi pin;
|
||||
struct ipu6_fw_isys_error_info_abi error_info;
|
||||
u32 timestamp[2];
|
||||
u8 stream_handle;
|
||||
u8 type;
|
||||
u8 pin_id;
|
||||
u8 reserved;
|
||||
u32 reserved2;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_isys_proxy_error_info_abi - ISYS proxy error
|
||||
* @error: error code if something went wrong
|
||||
* @error_details: depending on error code, it may contain additional error info
|
||||
*/
|
||||
struct ipu6_fw_isys_proxy_error_info_abi {
|
||||
u32 error;
|
||||
u32 error_details;
|
||||
};
|
||||
|
||||
struct ipu6_fw_isys_proxy_resp_info_abi {
|
||||
u32 request_id;
|
||||
struct ipu6_fw_isys_proxy_error_info_abi error_info;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_proxy_write_queue_token - ISYS proxy write queue token
|
||||
* @request_id: update id for the specific proxy write request
|
||||
* @region_index: Region id for the proxy write request
|
||||
* @offset: Offset of the write request according to the base address
|
||||
* of the region
|
||||
* @value: Value that is requested to be written with the proxy write request
|
||||
*/
|
||||
struct ipu6_fw_proxy_write_queue_token {
|
||||
u32 request_id;
|
||||
u32 region_index;
|
||||
u32 offset;
|
||||
u32 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_resp_queue_token - ISYS response queue token
|
||||
* @resp_info: response info
|
||||
*/
|
||||
struct ipu6_fw_resp_queue_token {
|
||||
struct ipu6_fw_isys_resp_info_abi resp_info;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_send_queue_token - ISYS send queue token
|
||||
* @buf_handle: buffer handle
|
||||
* @payload: payload
|
||||
* @send_type: send_type
|
||||
* @stream_id: stream_id
|
||||
*/
|
||||
struct ipu6_fw_send_queue_token {
|
||||
u64 buf_handle;
|
||||
u32 payload;
|
||||
u16 send_type;
|
||||
u16 stream_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_proxy_resp_queue_token - ISYS proxy response queue token
|
||||
* @proxy_resp_info: proxy response info
|
||||
*/
|
||||
struct ipu6_fw_proxy_resp_queue_token {
|
||||
struct ipu6_fw_isys_proxy_resp_info_abi proxy_resp_info;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ipu6_fw_proxy_send_queue_token - SYS proxy send queue token
|
||||
* @request_id: request_id
|
||||
* @region_index: region_index
|
||||
* @offset: offset
|
||||
* @value: value
|
||||
*/
|
||||
struct ipu6_fw_proxy_send_queue_token {
|
||||
u32 request_id;
|
||||
u32 region_index;
|
||||
u32 offset;
|
||||
u32 value;
|
||||
};
|
||||
|
||||
void
|
||||
ipu6_fw_isys_dump_stream_cfg(struct device *dev,
|
||||
struct ipu6_fw_isys_stream_cfg_data_abi *cfg);
|
||||
void
|
||||
ipu6_fw_isys_dump_frame_buff_set(struct device *dev,
|
||||
struct ipu6_fw_isys_frame_buff_set_abi *buf,
|
||||
unsigned int outputs);
|
||||
int ipu6_fw_isys_init(struct ipu6_isys *isys, unsigned int num_streams);
|
||||
int ipu6_fw_isys_close(struct ipu6_isys *isys);
|
||||
int ipu6_fw_isys_simple_cmd(struct ipu6_isys *isys,
|
||||
const unsigned int stream_handle, u16 send_type);
|
||||
int ipu6_fw_isys_complex_cmd(struct ipu6_isys *isys,
|
||||
const unsigned int stream_handle,
|
||||
void *cpu_mapped_buf, dma_addr_t dma_mapped_buf,
|
||||
size_t size, u16 send_type);
|
||||
int ipu6_fw_isys_send_proxy_token(struct ipu6_isys *isys,
|
||||
unsigned int req_id,
|
||||
unsigned int index,
|
||||
unsigned int offset, u32 value);
|
||||
void ipu6_fw_isys_cleanup(struct ipu6_isys *isys);
|
||||
struct ipu6_fw_isys_resp_info_abi *
|
||||
ipu6_fw_isys_get_resp(void *context, unsigned int queue);
|
||||
void ipu6_fw_isys_put_resp(void *context, unsigned int queue);
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user