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drm/i915: Extract ilk_color_check()

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With everything else moved out of the way only ilk+
remains using _intel_color_check(). Streamline the logic
into ilk_color_check().

v2: Add some comments explaining we that we don't expose
    the full hardware capabilities currently (Matt)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190327155045.28446-9-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Ville Syrjälä 2019-03-27 17:50:43 +02:00
parent 1eb6315611
commit f65d5528c0
1 changed files with 33 additions and 43 deletions
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76
drivers/gpu/drm/i915/intel_color.c
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@ -883,6 +883,38 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
static int ilk_color_check(struct intel_crtc_state *crtc_state)
{
int ret;
ret = check_luts(crtc_state);
if (ret)
return ret;
crtc_state->gamma_enable =
crtc_state->base.gamma_lut &&
!crtc_state->c8_planes;
/*
* We don't expose the ctm on ilk-hsw currently,
* nor do we enable YCbCr output. Only hsw uses
* the csc for RGB limited range output.
*/
crtc_state->csc_enable =
ilk_csc_limited_range(crtc_state);
/* We don't expose fancy gamma modes on ilk-hsw currently */
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
crtc_state->csc_mode = 0;
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
return ret;
return 0;
}
static u32 bdw_gamma_mode(const struct intel_crtc_state *crtc_state)
{
if (!crtc_state->gamma_enable ||
@ -1007,48 +1039,6 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
static int _intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
bool limited_color_range = false;
int ret;
ret = check_luts(crtc_state);
if (ret)
return ret;
crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
!crtc_state->c8_planes;
if (INTEL_GEN(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
limited_color_range = crtc_state->limited_color_range;
crtc_state->csc_enable =
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
crtc_state->base.ctm || limited_color_range;
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
return ret;
crtc_state->csc_mode = 0;
if (!crtc_state->gamma_enable ||
crtc_state_is_legacy_gamma(crtc_state))
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
else
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
return 0;
}
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@ -1073,7 +1063,7 @@ void intel_color_init(struct intel_crtc *crtc)
else if (INTEL_GEN(dev_priv) >= 8)
dev_priv->display.color_check = bdw_color_check;
else
dev_priv->display.color_check = _intel_color_check;
dev_priv->display.color_check = ilk_color_check;
if (INTEL_GEN(dev_priv) >= 9)
dev_priv->display.color_commit = skl_color_commit;