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USB: ehci-fsl: fix regression on mpc5121e

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mpc5121e doesn't have system interface registers, accessing this
register address space cause the machine check exception and a
kernel crash:

...
Machine check in kernel mode.
Caused by (from SRR1=49030): Transfer error ack signal
Oops: Machine check, sig: 7 [#1]
MPC5121 ADS
Modules linked in:
NIP: c025fd60 LR: c0265bb4 CTR: 00000000
REGS: df82dac0 TRAP: 0200   Not tainted
(3.7.0-rc7-00641-g81e6c91)
MSR: 00049030 <EE,ME,IR,DR>  CR: 42002024  XER: 20000000
TASK = df824b70[1] 'swapper' THREAD: df82c000
GPR00: 00000000 df82db70 df824b70 df3ed0f0 00000003 00000000 00000000 00000000
GPR08: 00000020 32000000 c03550ec 20000000 22002028 00000000 c0003f5c 00000000
GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 c0423898 c0450000
GPR24: 00000077 00000002 e5086180 1c000c00 e5086000 df33ec00 00000003 df34e000
NIP [c025fd60] ehci_fsl_setup_phy+0xd0/0x354
LR [c0265bb4] ehci_fsl_setup+0x220/0x284
...

Fix it by checking 'have_sysif_regs' flag before register access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Anatolij Gustschin 2012-12-04 14:24:30 +01:00 committed by Greg Kroah-Hartman
parent 929473ea05
commit f66dea709c
1 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/usb/host/ehci-fsl.c
View File

@ -230,7 +230,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
switch (phy_mode) {
case FSL_USB2_PHY_ULPI:
if (pdata->controller_ver) {
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
setbits32(non_ehci + FSL_SOC_USB_CTRL,
ULPI_PHY_CLK_SEL);
@ -251,7 +251,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
if (pdata->controller_ver) {
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
@ -267,7 +267,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {
if (pdata->have_sysif_regs && pdata->controller_ver &&
(phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
@ -278,7 +279,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
if (phy_mode != FSL_USB2_PHY_ULPI)
if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
return 0;