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drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs

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The specification only requires DPT FB strides to be POT aligned, but
there seems to be also a minimum of 8 stride tile requirement. Scanning
out FBs with < 8 stride tiles will result in pipe faults (even though
the stride is POT aligned).

Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-10-imre.deak@intel.com
This commit is contained in:
Imre Deak 2021-05-06 19:19:29 +03:00
parent d3b4aa43ee
commit f6b044e4d9
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/i915/display/intel_fb.c
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@ -601,7 +601,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
unsigned int pitch_tiles)
{
if (intel_fb_needs_pot_stride_remap(fb))
return roundup_pow_of_two(pitch_tiles);
/*
* ADL_P, the only platform needing a POT stride has a minimum
* of 8 stride tiles.
*/
return roundup_pow_of_two(max(pitch_tiles, 8u));
else
return pitch_tiles;
}