arm-cci: Rearrange code for splitting PMU vs driver code
No functional changes, only code re-arrangements for easier split of the PMU code vs low level driver code. Extracts the port handling code to cci_probe_ports(). Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Suzuki K. Poulose
Will Deacon
parent
b1862199be
commit
f6b9e83ce0
@ -29,42 +29,29 @@
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#define DRIVER_NAME "CCI-400"
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#define DRIVER_NAME_PMU DRIVER_NAME " PMU"
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#define CCI_PORT_CTRL 0x0
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#define CCI_CTRL_STATUS 0xc
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#define CCI_ENABLE_SNOOP_REQ 0x1
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#define CCI_ENABLE_DVM_REQ 0x2
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#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
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static void __iomem *cci_ctrl_base;
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static unsigned long cci_ctrl_phys;
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struct cci_nb_ports {
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unsigned int nb_ace;
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unsigned int nb_ace_lite;
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};
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enum cci_ace_port_type {
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ACE_INVALID_PORT = 0x0,
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ACE_PORT,
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ACE_LITE_PORT,
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static const struct cci_nb_ports cci400_ports = {
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.nb_ace = 2,
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.nb_ace_lite = 3
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};
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struct cci_ace_port {
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void __iomem *base;
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unsigned long phys;
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enum cci_ace_port_type type;
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struct device_node *dn;
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static const struct of_device_id arm_cci_matches[] = {
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{.compatible = "arm,cci-400", .data = &cci400_ports },
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{},
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};
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static struct cci_ace_port *ports;
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static unsigned int nb_cci_ports;
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static void __iomem *cci_ctrl_base;
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static unsigned long cci_ctrl_phys;
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#ifdef CONFIG_HW_PERF_EVENTS
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#define DRIVER_NAME "CCI-400"
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#define DRIVER_NAME_PMU DRIVER_NAME " PMU"
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#define CCI_PMCR 0x0100
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#define CCI_PID2 0x0fe8
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@ -75,6 +62,47 @@ static unsigned long cci_ctrl_phys;
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#define CCI_PID2_REV_MASK 0xf0
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#define CCI_PID2_REV_SHIFT 4
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#define CCI_PMU_EVT_SEL 0x000
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#define CCI_PMU_CNTR 0x004
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#define CCI_PMU_CNTR_CTRL 0x008
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#define CCI_PMU_OVRFLW 0x00c
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#define CCI_PMU_OVRFLW_FLAG 1
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#define CCI_PMU_CNTR_BASE(idx) ((idx) * SZ_4K)
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#define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
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#define CCI_PMU_EVENT_MASK 0xff
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#define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
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#define CCI_PMU_EVENT_CODE(event) (event & 0x1f)
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#define CCI_PMU_MAX_HW_EVENTS 5 /* CCI PMU has 4 counters + 1 cycle counter */
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struct cci_pmu_hw_events {
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struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
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unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
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raw_spinlock_t pmu_lock;
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};
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struct cci_pmu {
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void __iomem *base;
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struct pmu pmu;
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int nr_irqs;
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int irqs[CCI_PMU_MAX_HW_EVENTS];
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unsigned long active_irqs;
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struct pmu_port_event_ranges *port_ranges;
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struct cci_pmu_hw_events hw_events;
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struct platform_device *plat_device;
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int num_events;
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atomic_t active_events;
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struct mutex reserve_mutex;
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cpumask_t cpus;
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};
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static struct cci_pmu *pmu;
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#define to_cci_pmu(c) (container_of(c, struct cci_pmu, pmu))
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/* Port ids */
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#define CCI_PORT_S0 0
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#define CCI_PORT_S1 1
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@ -89,17 +117,6 @@ static unsigned long cci_ctrl_phys;
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#define CCI_REV_R1 1
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#define CCI_REV_R1_PX 5
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#define CCI_PMU_EVT_SEL 0x000
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#define CCI_PMU_CNTR 0x004
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#define CCI_PMU_CNTR_CTRL 0x008
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#define CCI_PMU_OVRFLW 0x00c
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#define CCI_PMU_OVRFLW_FLAG 1
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#define CCI_PMU_CNTR_BASE(idx) ((idx) * SZ_4K)
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#define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
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/*
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* Instead of an event id to monitor CCI cycles, a dedicated counter is
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* provided. Use 0xff to represent CCI cycles and hope that no future revisions
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@ -109,12 +126,6 @@ enum cci400_perf_events {
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CCI_PMU_CYCLES = 0xff
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};
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#define CCI_PMU_EVENT_MASK 0xff
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#define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
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#define CCI_PMU_EVENT_CODE(event) (event & 0x1f)
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#define CCI_PMU_MAX_HW_EVENTS 5 /* CCI PMU has 4 counters + 1 cycle counter */
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#define CCI_PMU_CYCLE_CNTR_IDX 0
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#define CCI_PMU_CNTR0_IDX 1
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#define CCI_PMU_CNTR_LAST(cci_pmu) (CCI_PMU_CYCLE_CNTR_IDX + cci_pmu->num_events - 1)
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@ -172,60 +183,6 @@ static char *const pmu_names[] = {
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[CCI_REV_R1] = "CCI_400_r1",
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};
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struct cci_pmu_hw_events {
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struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
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unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
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raw_spinlock_t pmu_lock;
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};
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struct cci_pmu {
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void __iomem *base;
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struct pmu pmu;
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int nr_irqs;
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int irqs[CCI_PMU_MAX_HW_EVENTS];
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unsigned long active_irqs;
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struct pmu_port_event_ranges *port_ranges;
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struct cci_pmu_hw_events hw_events;
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struct platform_device *plat_device;
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int num_events;
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atomic_t active_events;
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struct mutex reserve_mutex;
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cpumask_t cpus;
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};
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static struct cci_pmu *pmu;
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#define to_cci_pmu(c) (container_of(c, struct cci_pmu, pmu))
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static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++)
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if (irq == irqs[i])
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return true;
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return false;
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}
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static int probe_cci_revision(void)
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{
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int rev;
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rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
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rev >>= CCI_PID2_REV_SHIFT;
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if (rev < CCI_REV_R1_PX)
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return CCI_REV_R0;
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else
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return CCI_REV_R1;
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}
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static struct pmu_port_event_ranges *port_range_by_rev(void)
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{
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int rev = probe_cci_revision();
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return &port_event_range[rev];
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}
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static int pmu_is_valid_slave_event(u8 ev_code)
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{
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return pmu->port_ranges->slave_min <= ev_code &&
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@ -265,6 +222,25 @@ static int pmu_validate_hw_event(u8 hw_event)
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return -ENOENT;
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}
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static int probe_cci_revision(void)
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{
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int rev;
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rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
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rev >>= CCI_PID2_REV_SHIFT;
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if (rev < CCI_REV_R1_PX)
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return CCI_REV_R0;
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else
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return CCI_REV_R1;
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}
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static struct pmu_port_event_ranges *port_range_by_rev(void)
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{
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int rev = probe_cci_revision();
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return &port_event_range[rev];
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}
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static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
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{
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return CCI_PMU_CYCLE_CNTR_IDX <= idx &&
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@ -902,6 +878,17 @@ static const struct of_device_id arm_cci_pmu_matches[] = {
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{},
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};
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static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++)
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if (irq == irqs[i])
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return true;
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return false;
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}
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static int cci_pmu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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@ -972,8 +959,65 @@ static int cci_platform_probe(struct platform_device *pdev)
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return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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}
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static struct platform_driver cci_pmu_driver = {
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.driver = {
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.name = DRIVER_NAME_PMU,
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.of_match_table = arm_cci_pmu_matches,
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},
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.probe = cci_pmu_probe,
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};
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static struct platform_driver cci_platform_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = arm_cci_matches,
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},
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.probe = cci_platform_probe,
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};
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static int __init cci_platform_init(void)
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{
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int ret;
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ret = platform_driver_register(&cci_pmu_driver);
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if (ret)
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return ret;
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return platform_driver_register(&cci_platform_driver);
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}
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#else /* !CONFIG_HW_PERF_EVENTS */
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static int __init cci_platform_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_HW_PERF_EVENTS */
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#define CCI_PORT_CTRL 0x0
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#define CCI_CTRL_STATUS 0xc
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#define CCI_ENABLE_SNOOP_REQ 0x1
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#define CCI_ENABLE_DVM_REQ 0x2
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#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
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enum cci_ace_port_type {
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ACE_INVALID_PORT = 0x0,
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ACE_PORT,
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ACE_LITE_PORT,
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};
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struct cci_ace_port {
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void __iomem *base;
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unsigned long phys;
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enum cci_ace_port_type type;
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struct device_node *dn;
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};
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static struct cci_ace_port *ports;
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static unsigned int nb_cci_ports;
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struct cpu_port {
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u64 mpidr;
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u32 port;
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@ -1293,36 +1337,20 @@ int notrace __cci_control_port_by_index(u32 port, bool enable)
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}
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EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
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static const struct cci_nb_ports cci400_ports = {
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.nb_ace = 2,
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.nb_ace_lite = 3
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};
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static const struct of_device_id arm_cci_matches[] = {
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{.compatible = "arm,cci-400", .data = &cci400_ports },
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{},
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};
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static const struct of_device_id arm_cci_ctrl_if_matches[] = {
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{.compatible = "arm,cci-400-ctrl-if", },
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{},
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};
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static int cci_probe(void)
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static int cci_probe_ports(struct device_node *np)
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{
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struct cci_nb_ports const *cci_config;
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int ret, i, nb_ace = 0, nb_ace_lite = 0;
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struct device_node *np, *cp;
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struct device_node *cp;
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struct resource res;
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const char *match_str;
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bool is_ace;
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np = of_find_matching_node(NULL, arm_cci_matches);
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if (!np)
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return -ENODEV;
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if (!of_device_is_available(np))
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return -ENODEV;
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cci_config = of_match_node(arm_cci_matches, np)->data;
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if (!cci_config)
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@ -1334,17 +1362,6 @@ static int cci_probe(void)
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if (!ports)
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return -ENOMEM;
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ret = of_address_to_resource(np, 0, &res);
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if (!ret) {
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cci_ctrl_base = ioremap(res.start, resource_size(&res));
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cci_ctrl_phys = res.start;
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}
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if (ret || !cci_ctrl_base) {
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WARN(1, "unable to ioremap CCI ctrl\n");
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ret = -ENXIO;
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goto memalloc_err;
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}
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for_each_child_of_node(np, cp) {
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if (!of_match_node(arm_cci_ctrl_if_matches, cp))
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continue;
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@ -1404,12 +1421,31 @@ static int cci_probe(void)
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sync_cache_w(&cpu_port);
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__sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
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pr_info("ARM CCI driver probed\n");
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return 0;
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}
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memalloc_err:
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static int cci_probe(void)
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{
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int ret;
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struct device_node *np;
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struct resource res;
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kfree(ports);
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return ret;
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np = of_find_matching_node(NULL, arm_cci_matches);
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if(!np || !of_device_is_available(np))
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return -ENODEV;
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ret = of_address_to_resource(np, 0, &res);
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if (!ret) {
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cci_ctrl_base = ioremap(res.start, resource_size(&res));
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cci_ctrl_phys = res.start;
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}
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if (ret || !cci_ctrl_base) {
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WARN(1, "unable to ioremap CCI ctrl\n");
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return -ENXIO;
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}
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return cci_probe_ports(np);
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}
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static int cci_init_status = -EAGAIN;
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@ -1427,42 +1463,6 @@ static int cci_init(void)
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return cci_init_status;
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}
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#ifdef CONFIG_HW_PERF_EVENTS
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static struct platform_driver cci_pmu_driver = {
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.driver = {
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.name = DRIVER_NAME_PMU,
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.of_match_table = arm_cci_pmu_matches,
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},
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.probe = cci_pmu_probe,
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};
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static struct platform_driver cci_platform_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = arm_cci_matches,
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},
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.probe = cci_platform_probe,
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};
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static int __init cci_platform_init(void)
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{
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int ret;
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ret = platform_driver_register(&cci_pmu_driver);
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if (ret)
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return ret;
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return platform_driver_register(&cci_platform_driver);
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}
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#else
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static int __init cci_platform_init(void)
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{
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return 0;
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}
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#endif
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/*
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* To sort out early init calls ordering a helper function is provided to
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* check if the CCI driver has beed initialized. Function check if the driver
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