drm/i915: fix clear mask in GEN7_MISCCPCTL update
GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse. The bug was introduced during conversion to intel_uncore_rmw helper. Suggested-by: Matt Roper <matthew.d.roper@intel.com> Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates") Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221017085525.3898649-1-andrzej.hajda@intel.com
This commit is contained in:
parent
80c1fb2ee7
commit
f74354670f
@ -1052,8 +1052,8 @@ static void ivb_parity_work(struct work_struct *work)
|
||||
if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
|
||||
goto out;
|
||||
|
||||
misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE,
|
||||
0);
|
||||
misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
|
||||
GEN7_DOP_CLOCK_GATE_ENABLE, 0);
|
||||
intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
|
||||
|
||||
while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
|
||||
|
@ -4321,8 +4321,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
|
||||
u32 val;
|
||||
|
||||
/* WaTempDisableDOPClkGating:bdw */
|
||||
misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE,
|
||||
0);
|
||||
misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
|
||||
GEN7_DOP_CLOCK_GATE_ENABLE, 0);
|
||||
|
||||
val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
|
||||
val &= ~L3_PRIO_CREDITS_MASK;
|
||||
|
Loading…
x
Reference in New Issue
Block a user