PCI: Fix whitespace, capitalization, and spelling errors
Fix whitespace, capitalization, and spelling errors. No functional change. I know "busses" is not an error, but "buses" was more common, so I used it consistently. Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus()) Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Bjorn Helgaas
@ -198,7 +198,7 @@ static int __pci_bus_find_cap_start(struct pci_bus *bus,
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* pci_find_capability - query for devices' capabilities
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* @dev: PCI device to query
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* @cap: capability code
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*
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@ -207,12 +207,12 @@ static int __pci_bus_find_cap_start(struct pci_bus *bus,
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_PCIX PCI-X
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* %PCI_CAP_ID_EXP PCI Express
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*/
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@ -228,13 +228,13 @@ int pci_find_capability(struct pci_dev *dev, int cap)
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}
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/**
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* pci_bus_find_capability - query for devices' capabilities
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* pci_bus_find_capability - query for devices' capabilities
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* @bus: the PCI bus to query
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* @devfn: PCI device to query
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* @cap: capability code
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*
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* Like pci_find_capability() but works for pci devices that do not have a
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* pci_dev structure set up yet.
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* pci_dev structure set up yet.
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*
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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@ -515,7 +515,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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return -EINVAL;
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/* Validate current state:
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* Can enter D0 from any state, but if we can only go deeper
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* Can enter D0 from any state, but if we can only go deeper
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* to sleep if we're already in a low power state
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*/
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if (state != PCI_D0 && dev->current_state <= PCI_D3cold
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@ -998,7 +998,7 @@ static void pci_restore_config_space(struct pci_dev *pdev)
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}
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}
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/**
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/**
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* pci_restore_state - Restore the saved state of a PCI device
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* @dev: - PCI device that we're dealing with
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*/
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@ -1030,7 +1030,7 @@ struct pci_saved_state {
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* the device saved state.
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* @dev: PCI device that we're dealing with
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*
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* Rerturn NULL if no state or error.
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* Return NULL if no state or error.
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*/
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struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
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{
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@ -1880,7 +1880,7 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
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* pci_dev_run_wake - Check if device can generate run-time wake-up events.
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* @dev: Device to check.
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*
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* Return true if the device itself is cabable of generating wake-up events
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* Return true if the device itself is capable of generating wake-up events
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* (through the platform or using the native PCIe PME) or if the device supports
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* PME and one of its upstream bridges can generate wake-up events.
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*/
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@ -2447,7 +2447,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
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switch (pci_pcie_type(pdev)) {
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/*
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* PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
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* but since their primary inteface is PCI/X, we conservatively
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* but since their primary interface is PCI/X, we conservatively
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* handle them as we would a non-PCIe device.
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*/
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case PCI_EXP_TYPE_PCIE_BRIDGE:
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@ -2471,7 +2471,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
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/*
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* PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
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* implemented by the remaining PCIe types to indicate peer-to-peer
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* capabilities, but only when they are part of a multifunciton
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* capabilities, but only when they are part of a multifunction
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* device. The footnote for section 6.12 indicates the specific
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* PCIe types included here.
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*/
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@ -2486,7 +2486,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
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}
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/*
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* PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable
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* PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
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* to single function devices with the exception of downstream ports.
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*/
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return true;
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@ -2622,7 +2622,7 @@ void pci_release_region(struct pci_dev *pdev, int bar)
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*
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* If @exclusive is set, then the region is marked so that userspace
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* is explicitly not allowed to map the resource via /dev/mem or
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* sysfs MMIO access.
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* sysfs MMIO access.
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*
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* Returns 0 on success, or %EBUSY on error. A warning
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* message is also printed on failure.
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@ -2634,7 +2634,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_n
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if (pci_resource_len(pdev, bar) == 0)
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return 0;
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if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
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if (!request_region(pci_resource_start(pdev, bar),
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pci_resource_len(pdev, bar), res_name))
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@ -2694,7 +2694,7 @@ int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
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*
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* The key difference that _exclusive makes it that userspace is
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* explicitly not allowed to map the resource via /dev/mem or
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* sysfs.
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* sysfs.
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*/
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int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
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{
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@ -2799,7 +2799,7 @@ int pci_request_regions(struct pci_dev *pdev, const char *res_name)
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* successfully.
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*
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* pci_request_regions_exclusive() will mark the region so that
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* /dev/mem and the sysfs MMIO access will not be allowed.
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* /dev/mem and the sysfs MMIO access will not be allowed.
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*
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* Returns 0 on success, or %EBUSY on error. A warning
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* message is also printed on failure.
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@ -2967,7 +2967,7 @@ pci_set_mwi(struct pci_dev *dev)
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cmd |= PCI_COMMAND_INVALIDATE;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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@ -3292,7 +3292,7 @@ clear:
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*
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* NOTE: This causes the caller to sleep for twice the device power transition
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* cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
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* by devault (i.e. unless the @dev's d3_delay field has a different value).
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* by default (i.e. unless the @dev's d3_delay field has a different value).
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* Moreover, only devices in D0 can be reset by this function.
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*/
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static int pci_pm_reset(struct pci_dev *dev, int probe)
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@ -3341,7 +3341,7 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
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/*
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* PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
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* this to 2ms to ensure that we meet the minium requirement.
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* this to 2ms to ensure that we meet the minimum requirement.
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*/
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msleep(2);
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@ -3998,7 +3998,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
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return -EINVAL;
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v = ffs(mps) - 8;
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if (v > dev->pcie_mpss)
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if (v > dev->pcie_mpss)
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return -EINVAL;
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v <<= 5;
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