KVM: arm64: Refactor sys_regs.h,c for nVHE reuse
Refactor sys_regs.h and sys_regs.c to make it easier to reuse common code. It will be used in nVHE in a later patch. Note that the refactored code uses __inline_bsearch for find_reg instead of bsearch to avoid copying the bsearch code for nVHE. No functional change intended. Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210817081134.2918285-6-tabba@google.com
This commit is contained in:
Fuad Tabba
Marc Zyngier
parent
dabb1667d8
commit
f76f89e2f7
@ -1153,6 +1153,11 @@
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#define ICH_VTR_A3V_SHIFT 21
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#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
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#define ARM64_FEATURE_FIELD_BITS 4
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/* Create a mask for the feature bits of the specified feature. */
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#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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@ -44,10 +44,6 @@
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* 64bit interface.
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*/
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#define reg_to_encoding(x) \
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sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
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(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
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static bool read_from_write_only(struct kvm_vcpu *vcpu,
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struct sys_reg_params *params,
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const struct sys_reg_desc *r)
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@ -1026,8 +1022,6 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
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return true;
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}
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#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
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/* Read a sanitised cpufeature ID register by sys_reg_desc */
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static u64 read_id_reg(const struct kvm_vcpu *vcpu,
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struct sys_reg_desc const *r, bool raz)
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@ -1038,40 +1032,40 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
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switch (id) {
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case SYS_ID_AA64PFR0_EL1:
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if (!vcpu_has_sve(vcpu))
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val &= ~FEATURE(ID_AA64PFR0_SVE);
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val &= ~FEATURE(ID_AA64PFR0_AMU);
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val &= ~FEATURE(ID_AA64PFR0_CSV2);
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val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
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val &= ~FEATURE(ID_AA64PFR0_CSV3);
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val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
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break;
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case SYS_ID_AA64PFR1_EL1:
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val &= ~FEATURE(ID_AA64PFR1_MTE);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
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if (kvm_has_mte(vcpu->kvm)) {
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u64 pfr, mte;
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pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
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mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
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val |= FIELD_PREP(FEATURE(ID_AA64PFR1_MTE), mte);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
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}
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break;
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case SYS_ID_AA64ISAR1_EL1:
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if (!vcpu_has_ptrauth(vcpu))
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val &= ~(FEATURE(ID_AA64ISAR1_APA) |
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FEATURE(ID_AA64ISAR1_API) |
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FEATURE(ID_AA64ISAR1_GPA) |
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FEATURE(ID_AA64ISAR1_GPI));
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val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
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break;
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case SYS_ID_AA64DFR0_EL1:
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/* Limit debug to ARMv8.0 */
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val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
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val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6);
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/* Limit guests to PMUv3 for ARMv8.4 */
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val = cpuid_feature_cap_perfmon_field(val,
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ID_AA64DFR0_PMUVER_SHIFT,
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kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
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/* Hide SPE from guests */
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val &= ~FEATURE(ID_AA64DFR0_PMSVER);
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER);
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break;
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case SYS_ID_DFR0_EL1:
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/* Limit guests to PMUv3 for ARMv8.4 */
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@ -2106,23 +2100,6 @@ static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
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return 0;
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}
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static int match_sys_reg(const void *key, const void *elt)
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{
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const unsigned long pval = (unsigned long)key;
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const struct sys_reg_desc *r = elt;
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return pval - reg_to_encoding(r);
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}
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static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
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const struct sys_reg_desc table[],
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unsigned int num)
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{
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unsigned long pval = reg_to_encoding(params);
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return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
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}
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int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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@ -2365,13 +2342,8 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
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trace_kvm_handle_sys_reg(esr);
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params.Op0 = (esr >> 20) & 3;
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params.Op1 = (esr >> 14) & 0x7;
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params.CRn = (esr >> 10) & 0xf;
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params.CRm = (esr >> 1) & 0xf;
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params.Op2 = (esr >> 17) & 0x7;
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params = esr_sys64_to_params(esr);
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params.regval = vcpu_get_reg(vcpu, Rt);
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params.is_write = !(esr & 1);
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ret = emulate_sys_reg(vcpu, ¶ms);
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@ -11,6 +11,12 @@
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#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
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#define __ARM64_KVM_SYS_REGS_LOCAL_H__
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#include <linux/bsearch.h>
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#define reg_to_encoding(x) \
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sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
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(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
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struct sys_reg_params {
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u8 Op0;
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u8 Op1;
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@ -21,6 +27,14 @@ struct sys_reg_params {
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bool is_write;
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};
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#define esr_sys64_to_params(esr) \
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((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
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.Op1 = ((esr) >> 14) & 0x7, \
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.CRn = ((esr) >> 10) & 0xf, \
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.CRm = ((esr) >> 1) & 0xf, \
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.Op2 = ((esr) >> 17) & 0x7, \
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.is_write = !((esr) & 1) })
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struct sys_reg_desc {
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/* Sysreg string for debug */
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const char *name;
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@ -152,6 +166,23 @@ static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
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return i1->Op2 - i2->Op2;
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}
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static inline int match_sys_reg(const void *key, const void *elt)
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{
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const unsigned long pval = (unsigned long)key;
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const struct sys_reg_desc *r = elt;
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return pval - reg_to_encoding(r);
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}
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static inline const struct sys_reg_desc *
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find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
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unsigned int num)
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{
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unsigned long pval = reg_to_encoding(params);
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return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
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}
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const struct sys_reg_desc *find_reg_by_id(u64 id,
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struct sys_reg_params *params,
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const struct sys_reg_desc table[],
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