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arm64: dts: rockchip: USB2, USB3 Host, PCIe2 to Khadas Edge 2

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Khadas Edge 2 has 1x USB2 with hub, 1x USB3 Host and 1x USB-C.
This commit adds support for PCIe2, USB3 Host and USB2.

Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
Link: https://lore.kernel.org/r/4d22afd70e5583458f405f5170f67690584e7efa.1708381247.git.efectn@protonmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Muhammed Efe Cetin 2024-02-20 01:34:20 +03:00 committed by Heiko Stuebner
parent 4a3afe9cf3
commit f786eda805
1 changed files with 97 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

97
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
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@ -19,6 +19,33 @@
stdout-path = "serial2:1500000n8";
};
vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_2_vcc3v3_en>;
regulator-name = "vcc3v3_pcie_wl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@ -84,6 +111,14 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
&combphy0_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@ -130,6 +165,30 @@
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pcie2 {
pcie2_2_rst: pcie2-2-rst {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie2_2_vcc3v3_en: pcie2-2-vcc-en {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pcie2x1l2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_2_rst>;
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_wl>;
status = "okay";
};
&sdhci {
@ -480,3 +539,41 @@
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_xhci {
status = "okay";
};