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clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode

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Some GDSC client drivers require the GDSC mode to be switched dynamically
to HW mode at runtime to gain the power benefits. Typically such client
drivers require the GDSC to be brought up in SW mode initially to enable
the required dependent clocks and configure the hardware to proper state.
Once initial hardware set up is done, they switch the GDSC to HW mode to
save power. At the end of usecase, they switch the GDSC back to SW mode
and disable the GDSC.

Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and
get_hwmode_dev callbacks for GDSC's whose respective client drivers
require the GDSC mode to be switched dynamically at runtime using
dev_pm_genpd_set_hwmode() API.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20240624044809.17751-4-quic_jkona@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Jagadeesh Kona 2024-06-24 10:18:07 +05:30 committed by Ulf Hansson
parent 0155aaf95a
commit f7ccdaad61
2 changed files with 42 additions and 0 deletions
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41
drivers/clk/qcom/gdsc.c
View File

@ -363,6 +363,43 @@ static int gdsc_disable(struct generic_pm_domain *domain)
return 0;
}
static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode)
{
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
ret = gdsc_hwctrl(sc, mode);
if (ret)
return ret;
/*
* Wait for the GDSC to go through a power down and
* up cycle. If we poll the status register before the
* power cycle is finished we might read incorrect values.
*/
udelay(1);
/*
* When the GDSC is switched to HW mode, HW can disable the GDSC.
* When the GDSC is switched back to SW mode, the GDSC will be enabled
* again, hence we need to poll for GDSC to complete the power up.
*/
if (!mode)
return gdsc_poll_status(sc, GDSC_ON);
return 0;
}
static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev)
{
struct gdsc *sc = domain_to_gdsc(domain);
u32 val;
regmap_read(sc->regmap, sc->gdscr, &val);
return !!(val & HW_CONTROL_MASK);
}
static int gdsc_init(struct gdsc *sc)
{
u32 mask, val;
@ -451,6 +488,10 @@ static int gdsc_init(struct gdsc *sc)
sc->pd.power_off = gdsc_disable;
if (!sc->pd.power_on)
sc->pd.power_on = gdsc_enable;
if (sc->flags & HW_CTRL_TRIGGER) {
sc->pd.set_hwmode_dev = gdsc_set_hwmode;
sc->pd.get_hwmode_dev = gdsc_get_hwmode;
}
ret = pm_genpd_init(&sc->pd, NULL, !on);
if (ret)

1
drivers/clk/qcom/gdsc.h
View File

@ -67,6 +67,7 @@ struct gdsc {
#define ALWAYS_ON BIT(6)
#define RETAIN_FF_ENABLE BIT(7)
#define NO_RET_PERIPH BIT(8)
#define HW_CTRL_TRIGGER BIT(9)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;