ARM: sprd: DTS and bindings for v6.8-rc1
Unisoc ARM64 DTS and bindings changes are: - Fixed a few dtb_check warnings - Add bindings for a new SoC - UMS9620 - Fixed an issue on UMS512 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEFERWgJDWndUxbQqEP1wYyxGauyEFAmWNLpoACgkQP1wYyxGa uyFXSw/9Fp4cFyXza1YKAngvFoOdwRVWkX29kzrdApbsZOqZW5az4Mo245vsoOzH 0AiAViQuaJVYvTcPJmFrOetT/KBN7LmIxjAH6p2j1pTVj2AQX3ElQj+apY64S2up AWtZxw4yn2XF3TxRGUAiD9EZncXWFG/V7wtAvkp0RD8hL1Ll4FKdOzboPCtDmpQc T8CVp+Qq1NFa7gvPeYUFwS8dEm528EIsbQ2CLXJmAWc1ZDuBuYmnydkUhULnP6tS WRHS2YfnsrMAoMI5JG4XsESoP4iK9OQp6Fwx9AdXgsmT7I37sXaVeOwWZ9vxtGWm sBZyx0w7XXUqTcQSRuue119v0+XWcBrKLYvhpBOV6xWxFbkrFoUuPbhRHsYWWH7d EJjlTfc6ROwek4/lvkqRBAf7qH5FOd43+tHcON7TzoX6Ac57Y3LfckwAUihehGQI Xqs4RFNFdncpTG6RdFO9+uiBDWRFf2NTMkUtCEtyzqPGpKoPoVY8qTX0b2o6BTGE H/BudIBGuFwunbBQde1wT4KCJLn8bnvxCv5yhz2s46gpF4zIhMvd0Szw6gz0e/eD blhZ2BkJG/VwNeknFKQKOwPish1vULsEDueMTz2zDnB2gA/aROaQXjPfvMKNb8EW cQ7hkjdsDnhkvNesaX7KtY15S21FB3OU3IhnlIG5Tw4kPwIgoWc= =GtWr -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWT2moACgkQYKtH/8kJ UicFcw//VVx97jzuDUiFq4T2ItDOh5f7ljJ7xdT/X1+5Va+/r+ECOWv6brVkc8kw OFmyhxbjIpMFhu1OcVaKMVcU+wbd2H/b6aFOKzVC7zRiYtj/X4y1rgf/+Rh2ofGD /zWTbfEu7DLXV14r68r3EesmhDGGwqlcK8ApLy+P0zZCHEsKm3WHBe+w8d2SerNK 80mJ7AQXIeFAr1P05b5TNSOEEaajoYpwa6G37DVMfILtHscFV5vfiTzDULjyPkr0 oK4rCqX6GVONL7jHK6gAjAeGUYBypTP0LtklFbVbOidLELNldc9PTx7aGUv7eyPE Rde3ErqjoE7H38Axio1c6f61KIZogHDYXIqDnPEKwFHfvmA94Zq+2asOjF7gmIJ/ vDZAvGD48xvdQ9l5MOYMZl7San57r3lmoMGmmly7beJM6fPVqky9xhVHMZ3W8DNN steXqsLPUF9E2055/SNh5E1OtEsldHsV0ovpOxejKrGkQetshnk9lF0NT75Nkf6w 6DF2knDOAYZOZ5B5Jp49YTRAAHpQ2UJUKr1JZK/fOSEMVuNGdzeo7QyIh7rhELJu swFX8w+74mpq44E8LwaCaidL5m3UpbPyQxErRVwv7dN0uyHqW3MTfA+lNU1Ph72H MWBwLdWxbqGcRryL9ADp5NH4s30uVfFLXF2/GrAS2Os8Fl2v9FI= =gOpe -----END PGP SIGNATURE----- Merge tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux into soc/dt ARM: sprd: DTS and bindings for v6.8-rc1 Unisoc ARM64 DTS and bindings changes are: - Fixed a few dtb_check warnings - Add bindings for a new SoC - UMS9620 - Fixed an issue on UMS512 * tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux: arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings arm64: dts: sprd: Add clock reference for pll2 on UMS512 arm64: dts: sprd: Removed unused clock references from etm nodes arm64: dts: sprd: Add support for Unisoc's UMS9620 dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 arm64: dts: sprd: fix the cpu node for UMS512 Link: https://lore.kernel.org/r/20231228084958.1439115-1-chunyan.zhang@unisoc.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f81647e761
@ -35,6 +35,11 @@ properties:
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- sprd,ums512-1h10
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- const: sprd,ums512
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- items:
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- enum:
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- sprd,ums9620-2h10
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- const: sprd,ums9620
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additionalProperties: true
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...
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@ -2,4 +2,5 @@
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dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
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sp9860g-1h10.dtb \
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sp9863a-1h10.dtb \
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ums512-1h10.dtb
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ums512-1h10.dtb \
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ums9620-2h10.dtb
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@ -96,7 +96,7 @@
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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compatible = "arm,cortex-a75";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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@ -104,7 +104,7 @@
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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compatible = "arm,cortex-a75";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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@ -113,7 +113,7 @@
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idle-states {
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entry-method = "psci";
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CORE_PD: core-pd {
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CORE_PD: cpu-pd {
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compatible = "arm,idle-state";
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entry-latency-us = <4000>;
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exit-latency-us = <4000>;
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@ -291,6 +291,7 @@
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pll2: clock-controller@0 {
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compatible = "sprd,ums512-gc-pll";
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reg = <0x0 0x100>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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@ -682,8 +683,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f040000 0 0x1000>;
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cpu = <&CPU0>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -699,8 +700,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f140000 0 0x1000>;
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cpu = <&CPU1>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -716,8 +717,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f240000 0 0x1000>;
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cpu = <&CPU2>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -733,8 +734,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f340000 0 0x1000>;
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cpu = <&CPU3>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -750,8 +751,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f440000 0 0x1000>;
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cpu = <&CPU4>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -767,8 +768,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f540000 0 0x1000>;
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cpu = <&CPU5>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -784,8 +785,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f640000 0 0x1000>;
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cpu = <&CPU6>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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@ -801,8 +802,8 @@
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x3f740000 0 0x1000>;
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cpu = <&CPU7>;
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clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
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clock-names = "apb_pclk", "clk_cs", "cs_src";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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38
arch/arm64/boot/dts/sprd/ums9620-2h10.dts
Normal file
38
arch/arm64/boot/dts/sprd/ums9620-2h10.dts
Normal file
@ -0,0 +1,38 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS9620-2h10 board DTS file
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*
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* Copyright (C) 2023, Unisoc Inc.
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*/
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/dts-v1/;
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#include "ums9620.dtsi"
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/ {
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model = "Unisoc UMS9620-2H10 Board";
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compatible = "sprd,ums9620-2h10", "sprd,ums9620";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x00000000>;
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};
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chosen {
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stdout-path = "serial1:921600n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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245
arch/arm64/boot/dts/sprd/ums9620.dtsi
Normal file
245
arch/arm64/boot/dts/sprd/ums9620.dtsi
Normal file
@ -0,0 +1,245 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS9620 DTS file
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*
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* Copyright (C) 2023, Unisoc Inc.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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};
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idle-states {
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entry-method = "psci";
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LIT_CORE_PD: cpu-pd-lit {
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compatible = "arm,idle-state";
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entry-latency-us = <1000>;
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exit-latency-us = <500>;
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min-residency-us = <2500>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010000>;
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};
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BIG_CORE_PD: cpu-pd-big {
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compatible = "arm,idle-state";
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entry-latency-us = <4000>;
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exit-latency-us = <4000>;
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min-residency-us = <10000>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc: soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@12000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x12000000 0 0x20000>, /* GICD */
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<0x0 0x12040000 0 0x100000>; /* GICR */
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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redistributor-stride = <0x0 0x20000>; /* 128KB stride */
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#redistributor-regions = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apb@20200000 {
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compatible = "simple-bus";
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ranges = <0 0 0x20200000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0 {
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compatible = "sprd,ums9620-uart",
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"sprd,sc9836-uart";
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reg = <0 0x100>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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uart1: serial@10000 {
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compatible = "sprd,ums9620-uart",
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"sprd,sc9836-uart";
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reg = <0x10000 0x100>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext_26m: clk-26m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "ext-26m";
|
||||
};
|
||||
|
||||
ext_4m: clk-4m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <4000000>;
|
||||
clock-output-names = "ext-4m";
|
||||
};
|
||||
|
||||
ext_32k: clk-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ext-32k";
|
||||
};
|
||||
|
||||
rco_100m: clk-100m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "rco-100m";
|
||||
};
|
||||
|
||||
dphy_312m5: dphy-312m5 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <312500000>;
|
||||
clock-output-names = "dphy-312m5";
|
||||
};
|
||||
|
||||
dphy_416m7: dphy-416m7 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <416700000>;
|
||||
clock-output-names = "dphy-416m7";
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user