crypto: hisilicon - Unify error detect process into qm
In error detect process, a lot of duplicate code can put into qm. We add two callback(get_dev_hw_err_status and log_dev_hw_err) into struct hisi_qm_err_ini to handle device error detect, meanwhile the qm error detect not changed. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Shukun Tan
Herbert Xu
parent
de3daf4b4a
commit
f826e6efb4
@ -709,14 +709,36 @@ static int hpre_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev)
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return 0;
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}
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static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)
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{
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const struct hpre_hw_error *err = hpre_hw_errors;
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struct device *dev = &qm->pdev->dev;
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while (err->msg) {
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if (err->int_msk & err_sts)
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dev_warn(dev, "%s [error status=0x%x] found\n",
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err->msg, err->int_msk);
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err++;
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}
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writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);
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}
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static u32 hpre_get_hw_err_status(struct hisi_qm *qm)
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{
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return readl(qm->io_base + HPRE_HAC_INT_STATUS);
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}
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static const struct hisi_qm_err_ini hpre_err_ini = {
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.hw_err_enable = hpre_hw_error_enable,
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.hw_err_disable = hpre_hw_error_disable,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT,
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.fe = 0,
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.msi = QM_DB_RANDOM_INVALID,
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.hw_err_enable = hpre_hw_error_enable,
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.hw_err_disable = hpre_hw_error_disable,
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.get_dev_hw_err_status = hpre_get_hw_err_status,
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.log_dev_hw_err = hpre_log_hw_error,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT,
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.fe = 0,
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.msi = QM_DB_RANDOM_INVALID,
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}
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};
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@ -926,64 +948,9 @@ static void hpre_remove(struct pci_dev *pdev)
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hisi_qm_uninit(qm);
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}
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static void hpre_log_hw_error(struct hpre *hpre, u32 err_sts)
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{
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const struct hpre_hw_error *err = hpre_hw_errors;
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struct device *dev = &hpre->qm.pdev->dev;
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while (err->msg) {
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if (err->int_msk & err_sts)
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dev_warn(dev, "%s [error status=0x%x] found\n",
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err->msg, err->int_msk);
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err++;
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}
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}
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static pci_ers_result_t hpre_hw_error_handle(struct hpre *hpre)
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{
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u32 err_sts;
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/* read err sts */
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err_sts = readl(hpre->qm.io_base + HPRE_HAC_INT_STATUS);
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if (err_sts) {
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hpre_log_hw_error(hpre, err_sts);
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/* clear error interrupts */
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writel(err_sts, hpre->qm.io_base + HPRE_HAC_SOURCE_INT);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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return PCI_ERS_RESULT_RECOVERED;
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}
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static pci_ers_result_t hpre_process_hw_error(struct pci_dev *pdev)
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{
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struct hpre *hpre = pci_get_drvdata(pdev);
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pci_ers_result_t qm_ret, hpre_ret;
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/* log qm error */
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qm_ret = hisi_qm_hw_error_handle(&hpre->qm);
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/* log hpre error */
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hpre_ret = hpre_hw_error_handle(hpre);
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return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
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hpre_ret == PCI_ERS_RESULT_NEED_RESET) ?
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PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
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}
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static pci_ers_result_t hpre_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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return hpre_process_hw_error(pdev);
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}
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static const struct pci_error_handlers hpre_err_handler = {
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.error_detected = hpre_error_detected,
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.error_detected = hisi_qm_dev_err_detected,
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};
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static struct pci_driver hpre_pci_driver = {
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@ -1886,13 +1886,7 @@ static void qm_hw_error_uninit(struct hisi_qm *qm)
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qm->ops->hw_error_uninit(qm);
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}
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/**
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* hisi_qm_hw_error_handle() - Handle qm non-fatal hardware errors.
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* @qm: The qm which has non-fatal hardware errors.
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*
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* Accelerators use this function to handle qm non-fatal hardware errors.
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*/
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pci_ers_result_t hisi_qm_hw_error_handle(struct hisi_qm *qm)
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static pci_ers_result_t qm_hw_error_handle(struct hisi_qm *qm)
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{
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if (!qm->ops->hw_error_handle) {
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dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
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@ -1901,7 +1895,6 @@ pci_ers_result_t hisi_qm_hw_error_handle(struct hisi_qm *qm)
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return qm->ops->hw_error_handle(qm);
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}
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EXPORT_SYMBOL_GPL(hisi_qm_hw_error_handle);
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/**
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* hisi_qm_get_hw_version() - Get hardware version of a qm.
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@ -1964,6 +1957,68 @@ void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
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}
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EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
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static pci_ers_result_t qm_dev_err_handle(struct hisi_qm *qm)
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{
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u32 err_sts;
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if (!qm->err_ini->get_dev_hw_err_status) {
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dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
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return PCI_ERS_RESULT_NONE;
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}
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/* get device hardware error status */
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err_sts = qm->err_ini->get_dev_hw_err_status(qm);
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if (err_sts) {
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if (!qm->err_ini->log_dev_hw_err) {
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dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
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return PCI_ERS_RESULT_NEED_RESET;
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}
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qm->err_ini->log_dev_hw_err(qm, err_sts);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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return PCI_ERS_RESULT_RECOVERED;
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}
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static pci_ers_result_t qm_process_dev_error(struct pci_dev *pdev)
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{
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struct hisi_qm *qm = pci_get_drvdata(pdev);
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pci_ers_result_t qm_ret, dev_ret;
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/* log qm error */
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qm_ret = qm_hw_error_handle(qm);
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/* log device error */
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dev_ret = qm_dev_err_handle(qm);
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return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
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dev_ret == PCI_ERS_RESULT_NEED_RESET) ?
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PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
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}
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/**
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* hisi_qm_dev_err_detected() - Get device and qm error status then log it.
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* @pdev: The PCI device which need report error.
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* @state: The connectivity between CPU and device.
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*
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* We register this function into PCIe AER handlers, It will report device or
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* qm hardware error status when error occur.
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*/
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pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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if (pdev->is_virtfn)
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return PCI_ERS_RESULT_NONE;
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pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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return qm_process_dev_error(pdev);
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}
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EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
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MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
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@ -137,6 +137,8 @@ struct hisi_qm_err_info {
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struct hisi_qm_err_ini {
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void (*hw_err_enable)(struct hisi_qm *qm);
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void (*hw_err_disable)(struct hisi_qm *qm);
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u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
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void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
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struct hisi_qm_err_info err_info;
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};
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@ -227,11 +229,12 @@ int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
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int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
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int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
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int hisi_qm_debug_init(struct hisi_qm *qm);
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pci_ers_result_t hisi_qm_hw_error_handle(struct hisi_qm *qm);
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enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
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void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
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void hisi_qm_dev_err_init(struct hisi_qm *qm);
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void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
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pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state);
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struct hisi_acc_sgl_pool;
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struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
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@ -672,15 +672,48 @@ static void sec_debugfs_exit(struct sec_dev *sec)
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debugfs_remove_recursive(sec->qm.debug.debug_root);
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}
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static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
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{
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const struct sec_hw_error *errs = sec_hw_errors;
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struct device *dev = &qm->pdev->dev;
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u32 err_val;
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while (errs->msg) {
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if (errs->int_msk & err_sts) {
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dev_err(dev, "%s [error status=0x%x] found\n",
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errs->msg, errs->int_msk);
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if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
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err_val = readl(qm->io_base +
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SEC_CORE_SRAM_ECC_ERR_INFO);
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dev_err(dev, "multi ecc sram num=0x%x\n",
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SEC_ECC_NUM(err_val));
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dev_err(dev, "multi ecc sram addr=0x%x\n",
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SEC_ECC_ADDR(err_val));
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}
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}
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errs++;
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}
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writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
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}
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static u32 sec_get_hw_err_status(struct hisi_qm *qm)
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{
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return readl(qm->io_base + SEC_CORE_INT_STATUS);
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}
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static const struct hisi_qm_err_ini sec_err_ini = {
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.hw_err_enable = sec_hw_error_enable,
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.hw_err_disable = sec_hw_error_disable,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
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QM_ACC_WB_NOT_READY_TIMEOUT,
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.fe = 0,
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.msi = QM_DB_RANDOM_INVALID,
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.hw_err_enable = sec_hw_error_enable,
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.hw_err_disable = sec_hw_error_disable,
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.get_dev_hw_err_status = sec_get_hw_err_status,
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.log_dev_hw_err = sec_log_hw_error,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
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QM_ACC_WB_NOT_READY_TIMEOUT,
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.fe = 0,
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.msi = QM_DB_RANDOM_INVALID,
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}
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};
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@ -963,84 +996,8 @@ static void sec_remove(struct pci_dev *pdev)
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sec_qm_uninit(qm);
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}
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static void sec_log_hw_error(struct sec_dev *sec, u32 err_sts)
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{
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const struct sec_hw_error *errs = sec_hw_errors;
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struct device *dev = &sec->qm.pdev->dev;
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u32 err_val;
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while (errs->msg) {
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if (errs->int_msk & err_sts) {
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dev_err(dev, "%s [error status=0x%x] found\n",
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errs->msg, errs->int_msk);
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if (SEC_CORE_INT_STATUS_M_ECC & err_sts) {
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err_val = readl(sec->qm.io_base +
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SEC_CORE_SRAM_ECC_ERR_INFO);
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dev_err(dev, "multi ecc sram num=0x%x\n",
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SEC_ECC_NUM(err_val));
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dev_err(dev, "multi ecc sram addr=0x%x\n",
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SEC_ECC_ADDR(err_val));
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}
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}
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errs++;
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}
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}
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static pci_ers_result_t sec_hw_error_handle(struct sec_dev *sec)
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{
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u32 err_sts;
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/* read err sts */
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err_sts = readl(sec->qm.io_base + SEC_CORE_INT_STATUS);
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if (err_sts) {
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sec_log_hw_error(sec, err_sts);
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/* clear error interrupts */
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writel(err_sts, sec->qm.io_base + SEC_CORE_INT_SOURCE);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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return PCI_ERS_RESULT_RECOVERED;
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}
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static pci_ers_result_t sec_process_hw_error(struct pci_dev *pdev)
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{
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struct sec_dev *sec = pci_get_drvdata(pdev);
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pci_ers_result_t qm_ret, sec_ret;
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if (!sec) {
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pci_err(pdev, "Can't recover error during device init\n");
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return PCI_ERS_RESULT_NONE;
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}
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/* log qm error */
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qm_ret = hisi_qm_hw_error_handle(&sec->qm);
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/* log sec error */
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sec_ret = sec_hw_error_handle(sec);
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return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
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sec_ret == PCI_ERS_RESULT_NEED_RESET) ?
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PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
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}
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static pci_ers_result_t sec_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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if (pdev->is_virtfn)
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return PCI_ERS_RESULT_NONE;
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pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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return sec_process_hw_error(pdev);
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}
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static const struct pci_error_handlers sec_err_handler = {
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.error_detected = sec_error_detected,
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.error_detected = hisi_qm_dev_err_detected,
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};
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static struct pci_driver sec_pci_driver = {
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@ -68,8 +68,8 @@
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#define HZIP_CORE_INT_RAS_NFE_ENB 0x301164
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#define HZIP_CORE_INT_RAS_FE_ENB 0x301168
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#define HZIP_CORE_INT_RAS_NFE_ENABLE 0x7FE
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#define SRAM_ECC_ERR_NUM_SHIFT 16
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#define SRAM_ECC_ERR_ADDR_SHIFT 24
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#define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16
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#define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24
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#define HZIP_CORE_INT_MASK_ALL GENMASK(10, 0)
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#define HZIP_COMP_CORE_NUM 2
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#define HZIP_DECOMP_CORE_NUM 6
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@ -647,14 +647,50 @@ static void hisi_zip_debugfs_exit(struct hisi_zip *hisi_zip)
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hisi_zip_debug_regs_clear(hisi_zip);
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}
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static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
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{
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const struct hisi_zip_hw_error *err = zip_hw_error;
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struct device *dev = &qm->pdev->dev;
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u32 err_val;
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while (err->msg) {
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if (err->int_msk & err_sts) {
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dev_err(dev, "%s [error status=0x%x] found\n",
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err->msg, err->int_msk);
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if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
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err_val = readl(qm->io_base +
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HZIP_CORE_SRAM_ECC_ERR_INFO);
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dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
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((err_val >>
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HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
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dev_err(dev, "hisi-zip multi ecc sram addr=0x%x\n",
|
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(err_val >>
|
||||
HZIP_SRAM_ECC_ERR_ADDR_SHIFT));
|
||||
}
|
||||
}
|
||||
err++;
|
||||
}
|
||||
|
||||
writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
|
||||
}
|
||||
|
||||
static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
|
||||
{
|
||||
return readl(qm->io_base + HZIP_CORE_INT_STATUS);
|
||||
}
|
||||
|
||||
static const struct hisi_qm_err_ini hisi_zip_err_ini = {
|
||||
.hw_err_enable = hisi_zip_hw_error_enable,
|
||||
.hw_err_disable = hisi_zip_hw_error_disable,
|
||||
.err_info = {
|
||||
.ce = QM_BASE_CE,
|
||||
.nfe = QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT,
|
||||
.fe = 0,
|
||||
.msi = QM_DB_RANDOM_INVALID,
|
||||
.hw_err_enable = hisi_zip_hw_error_enable,
|
||||
.hw_err_disable = hisi_zip_hw_error_disable,
|
||||
.get_dev_hw_err_status = hisi_zip_get_hw_err_status,
|
||||
.log_dev_hw_err = hisi_zip_log_hw_error,
|
||||
.err_info = {
|
||||
.ce = QM_BASE_CE,
|
||||
.nfe = QM_BASE_NFE |
|
||||
QM_ACC_WB_NOT_READY_TIMEOUT,
|
||||
.fe = 0,
|
||||
.msi = QM_DB_RANDOM_INVALID,
|
||||
}
|
||||
};
|
||||
|
||||
@ -906,85 +942,8 @@ static void hisi_zip_remove(struct pci_dev *pdev)
|
||||
hisi_zip_remove_from_list(hisi_zip);
|
||||
}
|
||||
|
||||
static void hisi_zip_log_hw_error(struct hisi_zip *hisi_zip, u32 err_sts)
|
||||
{
|
||||
const struct hisi_zip_hw_error *err = zip_hw_error;
|
||||
struct device *dev = &hisi_zip->qm.pdev->dev;
|
||||
u32 err_val;
|
||||
|
||||
while (err->msg) {
|
||||
if (err->int_msk & err_sts) {
|
||||
dev_warn(dev, "%s [error status=0x%x] found\n",
|
||||
err->msg, err->int_msk);
|
||||
|
||||
if (HZIP_CORE_INT_STATUS_M_ECC & err->int_msk) {
|
||||
err_val = readl(hisi_zip->qm.io_base +
|
||||
HZIP_CORE_SRAM_ECC_ERR_INFO);
|
||||
dev_warn(dev, "hisi-zip multi ecc sram num=0x%x\n",
|
||||
((err_val >> SRAM_ECC_ERR_NUM_SHIFT) &
|
||||
0xFF));
|
||||
dev_warn(dev, "hisi-zip multi ecc sram addr=0x%x\n",
|
||||
(err_val >> SRAM_ECC_ERR_ADDR_SHIFT));
|
||||
}
|
||||
}
|
||||
err++;
|
||||
}
|
||||
}
|
||||
|
||||
static pci_ers_result_t hisi_zip_hw_error_handle(struct hisi_zip *hisi_zip)
|
||||
{
|
||||
u32 err_sts;
|
||||
|
||||
/* read err sts */
|
||||
err_sts = readl(hisi_zip->qm.io_base + HZIP_CORE_INT_STATUS);
|
||||
|
||||
if (err_sts) {
|
||||
hisi_zip_log_hw_error(hisi_zip, err_sts);
|
||||
/* clear error interrupts */
|
||||
writel(err_sts, hisi_zip->qm.io_base + HZIP_CORE_INT_SOURCE);
|
||||
|
||||
return PCI_ERS_RESULT_NEED_RESET;
|
||||
}
|
||||
|
||||
return PCI_ERS_RESULT_RECOVERED;
|
||||
}
|
||||
|
||||
static pci_ers_result_t hisi_zip_process_hw_error(struct pci_dev *pdev)
|
||||
{
|
||||
struct hisi_zip *hisi_zip = pci_get_drvdata(pdev);
|
||||
struct device *dev = &pdev->dev;
|
||||
pci_ers_result_t qm_ret, zip_ret;
|
||||
|
||||
if (!hisi_zip) {
|
||||
dev_err(dev,
|
||||
"Can't recover ZIP-error occurred during device init\n");
|
||||
return PCI_ERS_RESULT_NONE;
|
||||
}
|
||||
|
||||
qm_ret = hisi_qm_hw_error_handle(&hisi_zip->qm);
|
||||
|
||||
zip_ret = hisi_zip_hw_error_handle(hisi_zip);
|
||||
|
||||
return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
|
||||
zip_ret == PCI_ERS_RESULT_NEED_RESET) ?
|
||||
PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
|
||||
}
|
||||
|
||||
static pci_ers_result_t hisi_zip_error_detected(struct pci_dev *pdev,
|
||||
pci_channel_state_t state)
|
||||
{
|
||||
if (pdev->is_virtfn)
|
||||
return PCI_ERS_RESULT_NONE;
|
||||
|
||||
dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
|
||||
if (state == pci_channel_io_perm_failure)
|
||||
return PCI_ERS_RESULT_DISCONNECT;
|
||||
|
||||
return hisi_zip_process_hw_error(pdev);
|
||||
}
|
||||
|
||||
static const struct pci_error_handlers hisi_zip_err_handler = {
|
||||
.error_detected = hisi_zip_error_detected,
|
||||
.error_detected = hisi_qm_dev_err_detected,
|
||||
};
|
||||
|
||||
static struct pci_driver hisi_zip_pci_driver = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user