hwspinlock/u8500: add hwspinlock driver
Add hwspinlock driver for U8500's Hsem hardware.
At this point only HSem's protocol 1 is used (i.e. no interrupts).
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
[ohad@wizery.com: adopt recent hwspin_lock_{un}register API changes]
[ohad@wizery.com: set the owner member of the driver]
[ohad@wizery.com: mark ->remove() function as __devexit]
[ohad@wizery.com: write commit log]
[ohad@wizery.com: small cleanups]
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
This commit is contained in:
Mathieu J. Poirier
Ohad Ben-Cohen
parent
300bab9770
commit
f84a8ecfca
@ -18,4 +18,15 @@ config HWSPINLOCK_OMAP
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If unsure, say N.
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config HSEM_U8500
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tristate "STE Hardware Semaphore functionality"
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depends on ARCH_U8500
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select HWSPINLOCK
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help
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Say y here to support the STE Hardware Semaphore functionality, which
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provides a synchronisation mechanism for the various processor on the
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SoC.
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If unsure, say N.
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endmenu
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@ -4,3 +4,4 @@
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obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o
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obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o
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obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o
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198
drivers/hwspinlock/u8500_hsem.c
Normal file
198
drivers/hwspinlock/u8500_hsem.c
Normal file
@ -0,0 +1,198 @@
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/*
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* u8500 HWSEM driver
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*
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* Copyright (C) 2010-2011 ST-Ericsson
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*
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* Implements u8500 semaphore handling for protocol 1, no interrupts.
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*
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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* Heavily borrowed from the work of :
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* Simon Que <sque@ti.com>
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* Hari Kanigeri <h-kanigeri2@ti.com>
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* Ohad Ben-Cohen <ohad@wizery.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/hwspinlock.h>
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#include <linux/platform_device.h>
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#include "hwspinlock_internal.h"
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/*
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* Implementation of STE's HSem protocol 1 without interrutps.
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* The only masterID we allow is '0x01' to force people to use
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* HSems for synchronisation between processors rather than processes
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* on the ARM core.
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*/
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#define U8500_MAX_SEMAPHORE 32 /* a total of 32 semaphore */
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#define RESET_SEMAPHORE (0) /* free */
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/*
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* CPU ID for master running u8500 kernel.
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* Hswpinlocks should only be used to synchonise operations
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* between the Cortex A9 core and the other CPUs. Hence
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* forcing the masterID to a preset value.
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*/
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#define HSEM_MASTER_ID 0x01
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#define HSEM_REGISTER_OFFSET 0x08
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#define HSEM_CTRL_REG 0x00
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#define HSEM_ICRALL 0x90
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#define HSEM_PROTOCOL_1 0x01
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static int u8500_hsem_trylock(struct hwspinlock *lock)
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{
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void __iomem *lock_addr = lock->priv;
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writel(HSEM_MASTER_ID, lock_addr);
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/* get only first 4 bit and compare to masterID.
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* if equal, we have the semaphore, otherwise
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* someone else has it.
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*/
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return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
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}
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static void u8500_hsem_unlock(struct hwspinlock *lock)
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{
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void __iomem *lock_addr = lock->priv;
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/* release the lock by writing 0 to it */
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writel(RESET_SEMAPHORE, lock_addr);
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}
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/*
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* u8500: what value is recommended here ?
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*/
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static void u8500_hsem_relax(struct hwspinlock *lock)
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{
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ndelay(50);
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}
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static const struct hwspinlock_ops u8500_hwspinlock_ops = {
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.trylock = u8500_hsem_trylock,
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.unlock = u8500_hsem_unlock,
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.relax = u8500_hsem_relax,
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};
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static int __devinit u8500_hsem_probe(struct platform_device *pdev)
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{
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struct hwspinlock_pdata *pdata = pdev->dev.platform_data;
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struct hwspinlock_device *bank;
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struct hwspinlock *hwlock;
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struct resource *res;
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void __iomem *io_base;
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int i, ret, num_locks = U8500_MAX_SEMAPHORE;
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ulong val;
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if (!pdata)
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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io_base = ioremap(res->start, resource_size(res));
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if (!io_base) {
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ret = -ENOMEM;
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goto free_state;
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}
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/* make sure protocol 1 is selected */
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val = readl(io_base + HSEM_CTRL_REG);
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writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
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/* clear all interrupts */
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writel(0xFFFF, io_base + HSEM_ICRALL);
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bank = kzalloc(sizeof(*bank) + num_locks * sizeof(*hwlock), GFP_KERNEL);
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if (!bank) {
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ret = -ENOMEM;
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goto iounmap_base;
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}
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platform_set_drvdata(pdev, bank);
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for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
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hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
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/* no pm needed for HSem but required to comply with hwspilock core */
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pm_runtime_enable(&pdev->dev);
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ret = hwspin_lock_register(bank, &pdev->dev, &u8500_hwspinlock_ops,
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pdata->base_id, num_locks);
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if (ret)
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goto reg_fail;
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return 0;
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reg_fail:
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pm_runtime_disable(&pdev->dev);
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kfree(bank);
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iounmap_base:
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iounmap(io_base);
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return ret;
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}
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static int __devexit u8500_hsem_remove(struct platform_device *pdev)
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{
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struct hwspinlock_device *bank = platform_get_drvdata(pdev);
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void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;
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int ret;
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/* clear all interrupts */
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writel(0xFFFF, io_base + HSEM_ICRALL);
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ret = hwspin_lock_unregister(bank);
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if (ret) {
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dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
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return ret;
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}
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pm_runtime_disable(&pdev->dev);
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iounmap(io_base);
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kfree(bank);
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return 0;
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}
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static struct platform_driver u8500_hsem_driver = {
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.probe = u8500_hsem_probe,
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.remove = __devexit_p(u8500_hsem_remove),
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.driver = {
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.name = "u8500_hsem",
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.owner = THIS_MODULE,
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},
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};
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static int __init u8500_hsem_init(void)
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{
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return platform_driver_register(&u8500_hsem_driver);
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}
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/* board init code might need to reserve hwspinlocks for predefined purposes */
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postcore_initcall(u8500_hsem_init);
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static void __exit u8500_hsem_exit(void)
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{
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platform_driver_unregister(&u8500_hsem_driver);
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}
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module_exit(u8500_hsem_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Hardware Spinlock driver for u8500");
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MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
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