PCI/ACPI: Implement _HPX Type 3 Setting Record
The _HPX Type 3 Setting Record is intended to be more generic and allow configuration of settings not possible with Type 2 records. For example, firmware could ensure that the completion timeout value is set accordingly throughout the PCI tree. Implement support for _HPX Type 3 Setting Records, which were added in the ACPI 6.3 spec. Link: https://lore.kernel.org/lkml/20190208162414.3996-4-mr.nuke.me@gmail.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Alexandru Gagniuc
Bjorn Helgaas
parent
87fcf12e84
commit
f873c51a15
@ -216,6 +216,64 @@ static acpi_status decode_type2_hpx_record(union acpi_object *record,
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return AE_OK;
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}
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static void parse_hpx3_register(struct hpx_type3 *hpx3_reg,
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union acpi_object *reg_fields)
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{
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hpx3_reg->device_type = reg_fields[0].integer.value;
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hpx3_reg->function_type = reg_fields[1].integer.value;
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hpx3_reg->config_space_location = reg_fields[2].integer.value;
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hpx3_reg->pci_exp_cap_id = reg_fields[3].integer.value;
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hpx3_reg->pci_exp_cap_ver = reg_fields[4].integer.value;
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hpx3_reg->pci_exp_vendor_id = reg_fields[5].integer.value;
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hpx3_reg->dvsec_id = reg_fields[6].integer.value;
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hpx3_reg->dvsec_rev = reg_fields[7].integer.value;
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hpx3_reg->match_offset = reg_fields[8].integer.value;
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hpx3_reg->match_mask_and = reg_fields[9].integer.value;
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hpx3_reg->match_value = reg_fields[10].integer.value;
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hpx3_reg->reg_offset = reg_fields[11].integer.value;
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hpx3_reg->reg_mask_and = reg_fields[12].integer.value;
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hpx3_reg->reg_mask_or = reg_fields[13].integer.value;
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}
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static acpi_status program_type3_hpx_record(struct pci_dev *dev,
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union acpi_object *record,
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const struct hotplug_program_ops *hp_ops)
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{
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union acpi_object *fields = record->package.elements;
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u32 desc_count, expected_length, revision;
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union acpi_object *reg_fields;
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struct hpx_type3 hpx3;
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int i;
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revision = fields[1].integer.value;
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switch (revision) {
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case 1:
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desc_count = fields[2].integer.value;
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expected_length = 3 + desc_count * 14;
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if (record->package.count != expected_length)
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return AE_ERROR;
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for (i = 2; i < expected_length; i++)
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if (fields[i].type != ACPI_TYPE_INTEGER)
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return AE_ERROR;
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for (i = 0; i < desc_count; i++) {
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reg_fields = fields + 3 + i * 14;
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parse_hpx3_register(&hpx3, reg_fields);
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hp_ops->program_type3(dev, &hpx3);
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}
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break;
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default:
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printk(KERN_WARNING
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"%s: Type 3 Revision %d record not supported\n",
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__func__, revision);
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return AE_ERROR;
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}
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return AE_OK;
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}
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static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle,
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const struct hotplug_program_ops *hp_ops)
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{
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@ -275,6 +333,11 @@ static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle,
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goto exit;
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hp_ops->program_type2(dev, &hpx2);
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break;
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case 3:
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status = program_type3_hpx_record(dev, record, hp_ops);
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if (ACPI_FAILURE(status))
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goto exit;
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break;
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default:
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printk(KERN_ERR "%s: Type %d record not supported\n",
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__func__, type);
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@ -2026,6 +2026,119 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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*/
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}
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static u16 hpx3_device_type(struct pci_dev *dev)
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{
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u16 pcie_type = pci_pcie_type(dev);
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const int pcie_to_hpx3_type[] = {
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[PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT,
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[PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END,
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[PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END,
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[PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC,
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[PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT,
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[PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM,
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[PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM,
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[PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE,
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[PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE,
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};
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if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type))
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return 0;
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return pcie_to_hpx3_type[pcie_type];
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}
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static u8 hpx3_function_type(struct pci_dev *dev)
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{
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if (dev->is_virtfn)
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return HPX_FN_SRIOV_VIRT;
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else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0)
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return HPX_FN_SRIOV_PHYS;
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else
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return HPX_FN_NORMAL;
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}
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static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id)
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{
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u8 cap_ver = hpx3_cap_id & 0xf;
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if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id)
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return true;
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else if (cap_ver == pcie_cap_id)
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return true;
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return false;
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}
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static void program_hpx_type3_register(struct pci_dev *dev,
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const struct hpx_type3 *reg)
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{
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u32 match_reg, write_reg, header, orig_value;
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u16 pos;
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if (!(hpx3_device_type(dev) & reg->device_type))
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return;
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if (!(hpx3_function_type(dev) & reg->function_type))
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return;
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switch (reg->config_space_location) {
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case HPX_CFG_PCICFG:
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pos = 0;
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break;
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case HPX_CFG_PCIE_CAP:
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pos = pci_find_capability(dev, reg->pci_exp_cap_id);
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if (pos == 0)
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return;
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break;
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case HPX_CFG_PCIE_CAP_EXT:
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pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id);
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if (pos == 0)
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return;
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pci_read_config_dword(dev, pos, &header);
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if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header),
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reg->pci_exp_cap_ver))
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return;
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break;
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case HPX_CFG_VEND_CAP: /* Fall through */
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case HPX_CFG_DVSEC: /* Fall through */
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default:
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pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location");
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return;
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}
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pci_read_config_dword(dev, pos + reg->match_offset, &match_reg);
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if ((match_reg & reg->match_mask_and) != reg->match_value)
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return;
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pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
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orig_value = write_reg;
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write_reg &= reg->reg_mask_and;
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write_reg |= reg->reg_mask_or;
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if (orig_value == write_reg)
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return;
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pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
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pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
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pos, orig_value, write_reg);
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}
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static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx3)
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{
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if (!hpx3)
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return;
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if (!pci_is_pcie(dev))
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return;
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program_hpx_type3_register(dev, hpx3);
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}
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
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{
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struct pci_host_bridge *host;
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@ -2210,6 +2323,7 @@ static void pci_configure_device(struct pci_dev *dev)
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.program_type0 = program_hpp_type0,
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.program_type1 = program_hpp_type1,
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.program_type2 = program_hpp_type2,
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.program_type3 = program_hpx_type3,
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};
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pci_configure_mps(dev);
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@ -124,10 +124,58 @@ struct hpp_type2 {
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u32 sec_unc_err_mask_or;
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};
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/*
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* _HPX PCI Express Setting Record (Type 3)
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*/
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struct hpx_type3 {
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u16 device_type;
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u16 function_type;
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u16 config_space_location;
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u16 pci_exp_cap_id;
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u16 pci_exp_cap_ver;
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u16 pci_exp_vendor_id;
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u16 dvsec_id;
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u16 dvsec_rev;
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u16 match_offset;
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u32 match_mask_and;
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u32 match_value;
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u16 reg_offset;
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u32 reg_mask_and;
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u32 reg_mask_or;
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};
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struct hotplug_program_ops {
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void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp);
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void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp);
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void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp);
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void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp);
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};
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enum hpx_type3_dev_type {
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HPX_TYPE_ENDPOINT = BIT(0),
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HPX_TYPE_LEG_END = BIT(1),
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HPX_TYPE_RC_END = BIT(2),
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HPX_TYPE_RC_EC = BIT(3),
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HPX_TYPE_ROOT_PORT = BIT(4),
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HPX_TYPE_UPSTREAM = BIT(5),
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HPX_TYPE_DOWNSTREAM = BIT(6),
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HPX_TYPE_PCI_BRIDGE = BIT(7),
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HPX_TYPE_PCIE_BRIDGE = BIT(8),
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};
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enum hpx_type3_fn_type {
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HPX_FN_NORMAL = BIT(0),
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HPX_FN_SRIOV_PHYS = BIT(1),
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HPX_FN_SRIOV_VIRT = BIT(2),
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};
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enum hpx_type3_cfg_loc {
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HPX_CFG_PCICFG = 0,
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HPX_CFG_PCIE_CAP = 1,
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HPX_CFG_PCIE_CAP_EXT = 2,
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HPX_CFG_VEND_CAP = 3,
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HPX_CFG_DVSEC = 4,
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HPX_CFG_MAX,
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};
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#ifdef CONFIG_ACPI
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