From dbf76c0d3da8d18a46f75130bdfae7b3b54407c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 23 Apr 2024 15:31:03 +0100 Subject: [PATCH 01/14] dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt-schema documentation and clock IDs for the high speed interface 0 HSI0 clock management unit. This is used (amongst others) for USB. While the usual (sed) script has been used to derive the linux clock IDs from the data sheet, one manual tweak was applied to fix a typo which we don't want to carry: HSI0_USPDPDBG_USER -> HSI0_USBDPDBG_USER (note USB vs USP). Signed-off-by: André Draszik Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240423-hsi0-gs101-v1-1-2c3ddb50c720@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 29 +++++++++- include/dt-bindings/clock/google,gs101.h | 54 +++++++++++++++++++ 2 files changed, 81 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 1d2bcea41c85..94dcc4f84c85 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,16 +30,17 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-hsi0 - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 clocks: minItems: 1 - maxItems: 3 + maxItems: 5 clock-names: minItems: 1 - maxItems: 3 + maxItems: 5 "#clock-cells": const: 1 @@ -72,6 +73,30 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: HSI0 bus clock (from CMU_TOP) + - description: DPGTC (from CMU_TOP) + - description: USB DRD controller clock (from CMU_TOP) + - description: USB Display Port debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: dpgtc + - const: usb31drd + - const: usbdpdbg + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 3dac3577788a..7a2006f0edf1 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -313,6 +313,60 @@ #define CLK_APM_PLL_DIV4_APM 70 #define CLK_APM_PLL_DIV16_APM 71 +/* CMU_HSI0 */ +#define CLK_FOUT_USB_PLL 1 +#define CLK_MOUT_PLL_USB 2 +#define CLK_MOUT_HSI0_ALT_USER 3 +#define CLK_MOUT_HSI0_BUS_USER 4 +#define CLK_MOUT_HSI0_DPGTC_USER 5 +#define CLK_MOUT_HSI0_TCXO_USER 6 +#define CLK_MOUT_HSI0_USB20_USER 7 +#define CLK_MOUT_HSI0_USB31DRD_USER 8 +#define CLK_MOUT_HSI0_USBDPDBG_USER 9 +#define CLK_MOUT_HSI0_BUS 10 +#define CLK_MOUT_HSI0_USB20_REF 11 +#define CLK_MOUT_HSI0_USB31DRD 12 +#define CLK_DOUT_HSI0_USB31DRD 13 +#define CLK_GOUT_HSI0_PCLK 14 +#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15 +#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16 +#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17 +#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18 +#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19 +#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20 +#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21 +#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22 +#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23 +#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24 +#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25 +#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26 +#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27 +#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28 +#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31 +#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32 +#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33 +#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34 +#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35 +#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36 +#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37 +#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38 +#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39 +#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40 +#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41 +#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42 +#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43 +#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44 +#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45 +#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46 +#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49 +#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50 +#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51 +#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52 + /* CMU_MISC */ #define CLK_MOUT_MISC_BUS_USER 1 #define CLK_MOUT_MISC_SSS_USER 2 From 01aea123b11c7ebbdd64b2df3a4a5a7ad86a460d Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 14:02:17 +0100 Subject: [PATCH 02/14] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt schema documentation and clock IDs for the High Speed Interface 2 (HSI2) clock management unit. This CMU feeds high speed interfaces such as PCIe and UFS. [AD: * keep CMUs in google,gs101.h sorted alphabetically * resolve minor merge conflicts in google,gs101-clock.yaml * s/ufs_embd/ufs s/mmc_card/mmc Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-1-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 26 ++++++++ include/dt-bindings/clock/google,gs101.h | 62 +++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 94dcc4f84c85..caf442ead24b 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -31,6 +31,7 @@ properties: - google,gs101-cmu-apm - google,gs101-cmu-misc - google,gs101-cmu-hsi0 + - google,gs101-cmu-hsi2 - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 @@ -97,6 +98,31 @@ allOf: - const: usb31drd - const: usbdpdbg + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-hsi2 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: High Speed Interface bus clock (from CMU_TOP) + - description: High Speed Interface pcie clock (from CMU_TOP) + - description: High Speed Interface ufs clock (from CMU_TOP) + - description: High Speed Interface mmc clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: pcie + - const: ufs + - const: mmc + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 7a2006f0edf1..442f9e9037dc 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -367,6 +367,68 @@ #define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51 #define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52 +/* CMU_HSI2 */ +#define CLK_MOUT_HSI2_BUS_USER 1 +#define CLK_MOUT_HSI2_MMC_CARD_USER 2 +#define CLK_MOUT_HSI2_PCIE_USER 3 +#define CLK_MOUT_HSI2_UFS_EMBD_USER 4 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10 +#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11 +#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12 +#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13 +#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14 +#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15 +#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16 +#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17 +#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29 +#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30 +#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31 +#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32 +#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33 +#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34 +#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39 +#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40 +#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41 +#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42 +#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43 +#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44 +#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45 +#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46 +#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55 +#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56 +#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57 +#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58 +#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59 +#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60 + /* CMU_MISC */ #define CLK_MOUT_MISC_BUS_USER 1 #define CLK_MOUT_MISC_SSS_USER 2 From 4982a4a2092ee9f7334d8f119a6a15d8165f7a04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Fri, 26 Apr 2024 11:03:05 +0100 Subject: [PATCH 03/14] arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu-hsi0 clock controller. It feeds USB. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-2-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index eddb6b326fde..9755a0bb70a1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1247,6 +1247,20 @@ }; }; + cmu_hsi0: clock-controller@11000000 { + compatible = "google,gs101-cmu-hsi0"; + reg = <0x11000000 0x4000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, + <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; + clock-names = "oscclk", "bus", "dpgtc", "usb31drd", + "usbdpdbg"; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; From 86124c76683e31033180f1d31e7543863ce6d850 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 14:02:18 +0100 Subject: [PATCH 04/14] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..a0305555c4fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,6 +1267,18 @@ interrupts = ; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; From 14d15fcbe0f1fac5979a0b01160f3651340e38b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Mon, 29 Apr 2024 11:35:49 +0100 Subject: [PATCH 05/14] arm64: dts: exynos: gs101: add USB & USB-phy nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a0305555c4fd..e3b068c1a2c1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1261,6 +1261,47 @@ "usbdpdbg"; }; + usbdrd31_phy: phy@11100000 { + compatible = "google,gs101-usb31drd-phy"; + reg = <0x11100000 0x0100>, + <0x110f0000 0x0800>, + <0x110e0000 0x2800>; + reg-names = "phy", "pcs", "pma"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; + clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd31: usb@11110000 { + compatible = "google,gs101-dwusb3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; + clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x11110000 0x10000>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; + clock-names = "ref"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; From b93b3140e82a0e48442087c38346eabfb92c63af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Mon, 29 Apr 2024 11:35:50 +0100 Subject: [PATCH 06/14] arm64: dts: exynos: gs101-oriole: enable USB on this board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pixel 6 (Oriole) has a USB-C connector that can act as host or device. The USB role is detected dynamically using a MAX77759 TCPCI controller, but since there is no driver for the MAX77759, the role is defaulted to peripheral, without any endpoints / ports. This allows Oriole to be configured as a gadget, e.g. using configfs. As PMIC regulators are not implemented yet, we rely on USB LDOs being enabled by the bootloader. A placeholder regulator is used for now. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-2-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-oriole.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 6be15e990b65..03b2a6fdfdc4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -53,6 +53,12 @@ wakeup-source; }; }; + + /* TODO: Remove this once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "placeholder_reg"; + }; }; &ext_24_5m { @@ -106,6 +112,24 @@ status = "okay"; }; +&usbdrd31 { + status = "okay"; + vdd10-supply = <®_placeholder>; + vdd33-supply = <®_placeholder>; +}; + +&usbdrd31_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + maximum-speed = "super-speed-plus"; + status = "okay"; +}; + +&usbdrd31_phy { + status = "okay"; +}; + &usi_uart { samsung,clkreq-on; /* needed for UART mode */ status = "okay"; From 6d1434a7d95939d21cf300f73040e3e6a02e84f8 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 12:15:34 +0100 Subject: [PATCH 07/14] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update dt schema to include the gs101 hsi2 sysreg compatible. Signed-off-by: Peter Griffin Reviewed-by: André Draszik Acked-by: Rob Herring Link: https://lore.kernel.org/r/20240429111537.2369227-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index c0c6ce8fc786..3ca220582897 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - google,gs101-apm-sysreg + - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos3-sysreg @@ -72,6 +73,7 @@ allOf: compatible: contains: enum: + - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg From b5f5fe4b317c0fbda725a44d9c92d97930ad68e9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:43 +0100 Subject: [PATCH 08/14] arm64: dts: exynos: gs101: Add the hsi2 sysreg node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e3b068c1a2c1..9f7635a7928e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1320,6 +1320,12 @@ clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; From 4c65d7054b4ce8ceb30ba2b8aed90ceff6158d73 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:44 +0100 Subject: [PATCH 09/14] arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin Acked-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9f7635a7928e..16e1c474e8dd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1332,6 +1332,42 @@ interrupts = ; }; + ufs_0: ufs@14700000 { + compatible = "google,gs101-ufs"; + reg = <0x14700000 0x200>, + <0x14701100 0x200>, + <0x14780000 0xa000>, + <0x14600000 0x100>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; + }; + + ufs_0_phy: phy@14704000 { + compatible = "google,gs101-ufs-phy"; + reg = <0x14704000 0x3000>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&ext_24_5m>; + clock-names = "ref_clk"; + status = "disabled"; + }; + cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; reg = <0x17400000 0x8000>; From aaafb21e8190cd2bc8cadf3e0f017bc5c11bb109 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:45 +0100 Subject: [PATCH 10/14] arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node. ufs regulator is a stub until full s2mpg11 slave pmic support is added. The gpio defined is for the BOOTLD0 (gs101) signal connected to UFS_EN(s2mpg11) gpio enabled voltage rail for UFS. Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20240430141445.2688499-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 03b2a6fdfdc4..5e8ffe065081 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -59,6 +59,15 @@ compatible = "regulator-fixed"; regulator-name = "placeholder_reg"; }; + + /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ + ufs_0_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; &ext_24_5m { @@ -112,6 +121,15 @@ status = "okay"; }; +&ufs_0 { + status = "okay"; + vcc-supply = <&ufs_0_fixed_vcc_reg>; +}; + +&ufs_0_phy { + status = "okay"; +}; + &usbdrd31 { status = "okay"; vdd10-supply = <®_placeholder>; From 1665b303a00c1acb2fe126486c6256c755f0b7c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:46 +0100 Subject: [PATCH 11/14] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 16e1c474e8dd..09f6b33cf5b4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1390,6 +1390,8 @@ pinctrl_gpio_alive: pinctrl@174d0000 { compatible = "google,gs101-pinctrl"; reg = <0x174d0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", @@ -1401,6 +1403,8 @@ pinctrl_far_alive: pinctrl@174e0000 { compatible = "google,gs101-pinctrl"; reg = <0x174e0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", From 42e3f188b238b7fb1c42dee8b4dc4107cbb321e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:47 +0100 Subject: [PATCH 12/14] arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 09f6b33cf5b4..878e05a865a0 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -370,6 +370,8 @@ pinctrl_peric0: pinctrl@10840000 { compatible = "google,gs101-pinctrl"; reg = <0x10840000 0x00001000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; + clock-names = "pclk"; interrupts = ; }; @@ -914,6 +916,8 @@ pinctrl_peric1: pinctrl@10c40000 { compatible = "google,gs101-pinctrl"; reg = <0x10c40000 0x00001000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; + clock-names = "pclk"; interrupts = ; }; From 8120dc4656aedf86c24e1b5776f84fdd9f8ece80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:48 +0100 Subject: [PATCH 13/14] arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 878e05a865a0..9edda5b94abc 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1333,6 +1333,8 @@ pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; + clock-names = "pclk"; interrupts = ; }; From 4db286b0a29aa3576a401b637ac5910dac22117f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:49 +0100 Subject: [PATCH 14/14] arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add empty clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9edda5b94abc..a66e996666b8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1309,6 +1309,9 @@ pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; interrupts = ; }; @@ -1422,11 +1425,17 @@ pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; pinctrl_gsacore: pinctrl@17a80000 { compatible = "google,gs101-pinctrl"; reg = <0x17a80000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; cmu_top: clock-controller@1e080000 {