spi: omap2-mcspi: Fix DMA and FIFO event trigger size mismatch
[ Upstream commit baf8b9f8d260c55a86405f70a384c29cda888476 ] Commit b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length") broke SPI transfers where bits_per_word != 8. This is because of mimsatch between McSPI FIFO level event trigger size (SPI word length) and DMA request size(word length * maxburst). This leads to data corruption, lockup and errors like: spi1.0: EOW timed out Fix this by setting DMA maxburst size to 1 so that McSPI FIFO level event trigger size matches DMA request size. Fixes: b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length") Cc: stable@vger.kernel.org Reported-by: David Lechner <david@lechnology.com> Tested-by: David Lechner <david@lechnology.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -593,8 +593,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
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cfg.src_addr_width = width;
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cfg.dst_addr_width = width;
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cfg.src_maxburst = es;
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cfg.dst_maxburst = es;
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cfg.src_maxburst = 1;
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cfg.dst_maxburst = 1;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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