ARC fixes for 5.2-rc7
- hsdk platform unifying apertures - build system CROSS_COMPILE prefix -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdFqxcAAoJEGnX8d3iisJebpAP/3clqurFHD7pVwqzq5TImlDN u5t4GqMqPAVnbXArv5iiHJIGRwkcPHMoZB5qj/h303zKmNfwMQ4CAjQlDC2YDaGg 7dk6ovitiO+ZyH7F7viF8uU11cU2vUnuLZ1vP+KVEbu1mUConL4KYj9KMJUoO+VX KWdhsVEE+b/fQV1hXb/Jvqciithi3F+B7QKJPVSz39FHOpfQzCBq4yn6aMfKcSvR bAWog824yLApOLtfDlM2/+bR8gpxmacOBn5duutymBVoB2Tz9Pop/jcDcQJi836e b2iCia6vygOLv3XHFf4zf0VPIeCGmncT8P48QydUAiaYd7dalURkVETqm2YS9LR2 Pu9D5X6xPw6/0mHNVJ6gWcuDSfN/qHX++m8IDrSJF+3/f/12PBqm4HBIFy7GumVl nh99DJTo8LHIDcr5ZSavb8tmtSp1oL/3QFT7ydwP60XyOjlu8ZzP7/S/ycZHMKHV bX4sVyvtwtejQ0Gahmt8m+MxraI183yuFRZpIEXE2YbQfbMbPdIeUgiTiDQWphxs UCtnucepxKrGKLqpdWn9SxlGtO84Gl7/YROYfk+jJR7IwKK7blnfqzBL7JtfZ/CN X5qIYkqfyaqMWuQYpPRdZNqy1K76l30rR6LWLJ9BjXJNKtxv4eflPApG3RSIEwyY ijAp+v3+TvmZRSP+yQM7 =Mhn6 -----END PGP SIGNATURE----- Merge tag 'arc-5.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: - hsdk platform unifying apertures - build system CROSS_COMPILE prefix * tag 'arc-5.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat-hsdk]: unify memory apertures configuration ARC: build: Try to guess CROSS_COMPILE with cc-cross-prefix
This commit is contained in:
Linus Torvalds
commit
f8b5c72227
@ -5,6 +5,10 @@
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KBUILD_DEFCONFIG := nsim_hs_defconfig
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ifeq ($(CROSS_COMPILE),)
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CROSS_COMPILE := $(call cc-cross-prefix, arc-linux- arceb-linux-)
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endif
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cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__
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cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7
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cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38
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@ -32,8 +32,6 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
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#define ARC_PERIPHERAL_BASE 0xf0000000
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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@ -99,20 +97,167 @@ static void __init hsdk_enable_gpio_intc_wire(void)
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iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
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}
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static void __init hsdk_init_early(void)
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enum hsdk_axi_masters {
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M_HS_CORE = 0,
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M_HS_RTT,
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M_AXI_TUN,
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M_HDMI_VIDEO,
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M_HDMI_AUDIO,
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M_USB_HOST,
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M_ETHERNET,
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M_SDIO,
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M_GPU,
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M_DMAC_0,
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M_DMAC_1,
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M_DVFS
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};
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#define UPDATE_VAL 1
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/*
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* This is modified configuration of AXI bridge. Default settings
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* are specified in "Table 111 CREG Address Decoder register reset values".
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*
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* AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
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* Possible slaves are:
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* - 0 => no slave selected
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* - 1 => DDR controller port #1
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* - 2 => SRAM controller
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* - 3 => AXI tunnel
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* - 4 => EBI controller
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* - 5 => ROM controller
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* - 6 => AXI2APB bridge
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* - 7 => DDR controller port #2
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* - 8 => DDR controller port #3
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* - 9 => HS38x4 IOC
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* - 10 => HS38x4 DMI
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* AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
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*
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* Please read ARC HS Development IC Specification, section 17.2 for more
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* information about apertures configuration.
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*
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* m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
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* 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
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* 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
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* 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
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*/
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#define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m)))
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#define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
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#define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
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#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
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#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
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#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
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#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
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#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
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static void __init hsdk_init_memory_bridge(void)
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{
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u32 reg;
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/*
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* M_HS_CORE has one unique register - BOOT.
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* We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
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* aperture to be masked by 'boot mirror'.
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*/
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reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
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writel(reg, CREG_AXI_M_HS_CORE_BOOT);
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writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
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writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
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writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
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writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
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writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
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writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
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writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
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writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
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writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
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writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
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writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
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writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
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writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
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writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
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writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
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writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
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writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
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writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
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writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
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writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
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writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
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writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
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writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
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/*
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* PAE remapping for DMA clients does not work due to an RTL bug, so
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* CREG_PAE register must be programmed to all zeroes, otherwise it
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* will cause problems with DMA to/from peripherals even if PAE40 is
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* not used.
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*/
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writel(0x00000000, CREG_PAE);
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writel(UPDATE_VAL, CREG_PAE_UPDT);
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}
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/* Default is 1, which means "PAE offset = 4GByte" */
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writel_relaxed(0, (void __iomem *) CREG_PAE);
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/* Really apply settings made above */
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writel(1, (void __iomem *) CREG_PAE_UPDATE);
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static void __init hsdk_init_early(void)
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{
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hsdk_init_memory_bridge();
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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