ice: Print human-friendly PHY types
Provide human readable description of PHY capabilities and report_mode. Sample output: Old: [ 286.130405] ice 0000:16:00.0: get phy caps - report_mode = 0x2 [ 286.130409] ice 0000:16:00.0: phy_type_low = 0x108021020502000 [ 286.130412] ice 0000:16:00.0: phy_type_high = 0x0 [ 286.130415] ice 0000:16:00.0: caps = 0xc8 [ 286.130419] ice 0000:16:00.0: low_power_ctrl_an = 0x4 [ 286.130421] ice 0000:16:00.0: eee_cap = 0x0 [ 286.130424] ice 0000:16:00.0: eeer_value = 0x0 [ 286.130427] ice 0000:16:00.0: link_fec_options = 0xdf [ 286.130430] ice 0000:16:00.0: module_compliance_enforcement = 0x0 [ 286.130433] ice 0000:16:00.0: extended_compliance_code = 0xb [ 286.130435] ice 0000:16:00.0: module_type[0] = 0x11 [ 286.130438] ice 0000:16:00.0: module_type[1] = 0x1 [ 286.130441] ice 0000:16:00.0: module_type[2] = 0x0 New: [ 1128.297347] ice 0000:16:00.0: get phy caps dump [ 1128.297351] ice 0000:16:00.0: phy_caps_active: phy_type_low: 0x0108021020502000 [ 1128.297355] ice 0000:16:00.0: phy_caps_active: bit(13): 10G_SFI_DA [ 1128.297359] ice 0000:16:00.0: phy_caps_active: bit(20): 25GBASE_CR [ 1128.297362] ice 0000:16:00.0: phy_caps_active: bit(22): 25GBASE_CR1 [ 1128.297365] ice 0000:16:00.0: phy_caps_active: bit(29): 25G_AUI_C2C [ 1128.297368] ice 0000:16:00.0: phy_caps_active: bit(36): 50GBASE_CR2 [ 1128.297371] ice 0000:16:00.0: phy_caps_active: bit(41): 50G_LAUI2 [ 1128.297374] ice 0000:16:00.0: phy_caps_active: bit(51): 100GBASE_CR4 [ 1128.297377] ice 0000:16:00.0: phy_caps_active: bit(56): 100G_CAUI4 [ 1128.297380] ice 0000:16:00.0: phy_caps_active: phy_type_high: 0x0000000000000000 [ 1128.297383] ice 0000:16:00.0: phy_caps_active: report_mode = 0x4 [ 1128.297386] ice 0000:16:00.0: phy_caps_active: caps = 0xc8 [ 1128.297389] ice 0000:16:00.0: phy_caps_active: low_power_ctrl_an = 0x4 [ 1128.297392] ice 0000:16:00.0: phy_caps_active: eee_cap = 0x0 [ 1128.297394] ice 0000:16:00.0: phy_caps_active: eeer_value = 0x0 [ 1128.297397] ice 0000:16:00.0: phy_caps_active: link_fec_options = 0xdf [ 1128.297400] ice 0000:16:00.0: phy_caps_active: module_compliance_enforcement = 0x0 [ 1128.297402] ice 0000:16:00.0: phy_caps_active: extended_compliance_code = 0xb [ 1128.297405] ice 0000:16:00.0: phy_caps_active: module_type[0] = 0x11 [ 1128.297408] ice 0000:16:00.0: phy_caps_active: module_type[1] = 0x1 [ 1128.297411] ice 0000:16:00.0: phy_caps_active: module_type[2] = 0x0 Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Co-developed-by: Lukasz Plachno <lukasz.plachno@intel.com> Signed-off-by: Lukasz Plachno <lukasz.plachno@intel.com> Reviewed-by: Alexander Lobakin <alexandr.lobakin@intel.com> Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Anirudh Venkataramanan
Tony Nguyen
parent
26d1c571e1
commit
f8c74ca6d3
@ -8,6 +8,108 @@
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#define ICE_PF_RESET_WAIT_COUNT 300
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static const char * const ice_link_mode_str_low[] = {
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[0] = "100BASE_TX",
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[1] = "100M_SGMII",
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[2] = "1000BASE_T",
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[3] = "1000BASE_SX",
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[4] = "1000BASE_LX",
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[5] = "1000BASE_KX",
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[6] = "1G_SGMII",
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[7] = "2500BASE_T",
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[8] = "2500BASE_X",
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[9] = "2500BASE_KX",
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[10] = "5GBASE_T",
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[11] = "5GBASE_KR",
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[12] = "10GBASE_T",
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[13] = "10G_SFI_DA",
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[14] = "10GBASE_SR",
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[15] = "10GBASE_LR",
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[16] = "10GBASE_KR_CR1",
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[17] = "10G_SFI_AOC_ACC",
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[18] = "10G_SFI_C2C",
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[19] = "25GBASE_T",
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[20] = "25GBASE_CR",
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[21] = "25GBASE_CR_S",
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[22] = "25GBASE_CR1",
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[23] = "25GBASE_SR",
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[24] = "25GBASE_LR",
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[25] = "25GBASE_KR",
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[26] = "25GBASE_KR_S",
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[27] = "25GBASE_KR1",
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[28] = "25G_AUI_AOC_ACC",
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[29] = "25G_AUI_C2C",
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[30] = "40GBASE_CR4",
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[31] = "40GBASE_SR4",
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[32] = "40GBASE_LR4",
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[33] = "40GBASE_KR4",
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[34] = "40G_XLAUI_AOC_ACC",
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[35] = "40G_XLAUI",
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[36] = "50GBASE_CR2",
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[37] = "50GBASE_SR2",
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[38] = "50GBASE_LR2",
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[39] = "50GBASE_KR2",
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[40] = "50G_LAUI2_AOC_ACC",
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[41] = "50G_LAUI2",
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[42] = "50G_AUI2_AOC_ACC",
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[43] = "50G_AUI2",
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[44] = "50GBASE_CP",
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[45] = "50GBASE_SR",
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[46] = "50GBASE_FR",
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[47] = "50GBASE_LR",
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[48] = "50GBASE_KR_PAM4",
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[49] = "50G_AUI1_AOC_ACC",
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[50] = "50G_AUI1",
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[51] = "100GBASE_CR4",
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[52] = "100GBASE_SR4",
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[53] = "100GBASE_LR4",
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[54] = "100GBASE_KR4",
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[55] = "100G_CAUI4_AOC_ACC",
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[56] = "100G_CAUI4",
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[57] = "100G_AUI4_AOC_ACC",
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[58] = "100G_AUI4",
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[59] = "100GBASE_CR_PAM4",
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[60] = "100GBASE_KR_PAM4",
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[61] = "100GBASE_CP2",
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[62] = "100GBASE_SR2",
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[63] = "100GBASE_DR",
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};
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static const char * const ice_link_mode_str_high[] = {
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[0] = "100GBASE_KR2_PAM4",
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[1] = "100G_CAUI2_AOC_ACC",
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[2] = "100G_CAUI2",
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[3] = "100G_AUI2_AOC_ACC",
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[4] = "100G_AUI2",
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};
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/**
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* ice_dump_phy_type - helper function to dump phy_type
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* @hw: pointer to the HW structure
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* @low: 64 bit value for phy_type_low
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* @high: 64 bit value for phy_type_high
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* @prefix: prefix string to differentiate multiple dumps
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*/
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static void
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ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
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{
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ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
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for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
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if (low & BIT_ULL(i))
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ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
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prefix, i, ice_link_mode_str_low[i]);
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}
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ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
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for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
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if (high & BIT_ULL(i))
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ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
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prefix, i, ice_link_mode_str_high[i]);
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}
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}
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/**
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* ice_set_mac_type - Sets MAC type
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* @hw: pointer to the HW structure
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@ -183,6 +285,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
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struct ice_aqc_get_phy_caps *cmd;
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u16 pcaps_size = sizeof(*pcaps);
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struct ice_aq_desc desc;
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const char *prefix;
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struct ice_hw *hw;
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int status;
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@ -204,29 +307,48 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
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cmd->param0 |= cpu_to_le16(report_mode);
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status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
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ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
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report_mode);
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ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
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(unsigned long long)le64_to_cpu(pcaps->phy_type_low));
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ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
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(unsigned long long)le64_to_cpu(pcaps->phy_type_high));
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ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
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ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
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switch (report_mode) {
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case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
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prefix = "phy_caps_media";
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break;
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case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
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prefix = "phy_caps_no_media";
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break;
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case ICE_AQC_REPORT_ACTIVE_CFG:
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prefix = "phy_caps_active";
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break;
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case ICE_AQC_REPORT_DFLT_CFG:
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prefix = "phy_caps_default";
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break;
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default:
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prefix = "phy_caps_invalid";
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}
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ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
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le64_to_cpu(pcaps->phy_type_high), prefix);
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ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
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prefix, report_mode);
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ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
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ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
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pcaps->low_power_ctrl_an);
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ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
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ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
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pcaps->eee_cap);
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ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
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pcaps->eeer_value);
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ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
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pcaps->link_fec_options);
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ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
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pcaps->module_compliance_enforcement);
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ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
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pcaps->extended_compliance_code);
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ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
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prefix, pcaps->module_compliance_enforcement);
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ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
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prefix, pcaps->extended_compliance_code);
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ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
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pcaps->module_type[0]);
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ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
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pcaps->module_type[1]);
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ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
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ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
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pcaps->module_type[2]);
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if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
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