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drm/xe/guc: s/xe_guc_send_mmio/xe_guc_mmio_send

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Now aligns with the xe_guc_ct_send naming.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Philippe Lecluse <philippe.lecluse1@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matthew Brost 2023-01-12 17:25:32 -05:00 committed by Rodrigo Vivi
parent 99c821b00b
commit f900725af8
4 changed files with 6 additions and 6 deletions
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6
drivers/gpu/drm/xe/xe_guc.c
View File

@ -599,7 +599,7 @@ int xe_guc_suspend(struct xe_guc *guc)
XE_GUC_ACTION_CLIENT_SOFT_RESET,
};
ret = xe_guc_send_mmio(guc, action, ARRAY_SIZE(action));
ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
if (ret) {
drm_err(&guc_to_xe(guc)->drm,
"GuC suspend: CLIENT_SOFT_RESET fail: %d!\n", ret);
@ -630,7 +630,7 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
#define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)
#define MEDIA_SOFT_SCRATCH_COUNT 4
int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
{
struct xe_device *xe = guc_to_xe(guc);
struct xe_gt *gt = guc_to_gt(guc);
@ -747,7 +747,7 @@ static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val)
XE_BUG_ON(len == 1 && upper_32_bits(val));
/* Self config must go over MMIO */
ret = xe_guc_send_mmio(guc, request, ARRAY_SIZE(request));
ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request));
if (unlikely(ret < 0))
return ret;

2
drivers/gpu/drm/xe/xe_guc.h
View File

@ -22,7 +22,7 @@ int xe_guc_enable_communication(struct xe_guc *guc);
int xe_guc_suspend(struct xe_guc *guc);
void xe_guc_notify(struct xe_guc *guc);
int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len);
int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);

2
drivers/gpu/drm/xe/xe_guc_ct.c
View File

@ -268,7 +268,7 @@ static int guc_ct_control_toggle(struct xe_guc_ct *ct, bool enable)
enable ? GUC_CTB_CONTROL_ENABLE :
GUC_CTB_CONTROL_DISABLE),
};
int ret = xe_guc_send_mmio(ct_to_guc(ct), request, ARRAY_SIZE(request));
int ret = xe_guc_mmio_send(ct_to_guc(ct), request, ARRAY_SIZE(request));
return ret > 0 ? -EPROTO : ret;
}

2
drivers/gpu/drm/xe/xe_guc_hwconfig.c
View File

@ -33,7 +33,7 @@ static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)
size,
};
return xe_guc_send_mmio(guc, action, ARRAY_SIZE(action));
return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
}
static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)