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ARM: dts: stm32: add RCC on STM32MP13x SoC family

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Enables Reset and Clocks Controller on STM32MP13

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Gabriel Fernandez 2022-02-23 10:18:19 +01:00 committed by Alexandre Torgue
parent 63058bfbda
commit f95634becd
4 changed files with 47 additions and 79 deletions
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116
arch/arm/boot/dts/stm32mp131.dtsi
View File

@ -4,6 +4,8 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
@ -52,62 +54,6 @@
};
};
clocks {
clk_axi: clk-axi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <266500000>;
};
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_pclk3: clk-pclk3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104438965>;
};
clk_pclk4: clk-pclk4 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <133250000>;
};
clk_pll4_p: clk-pll4_p {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clk_pll4_r: clk-pll4_r {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <99000000>;
};
clk_rtc_k: clk-rtc-k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
@ -155,7 +101,8 @@
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hsi>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
status = "disabled";
};
@ -170,7 +117,8 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMA1>;
resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@ -187,7 +135,8 @@
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMA2>;
resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@ -196,13 +145,27 @@
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x40>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMAMUX1>;
resets = <&rcc DMAMUX1_R>;
#dma-cells = <3>;
dma-masters = <&dma1 &dma2>;
dma-requests = <128>;
dma-channels = <16>;
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@ -213,14 +176,14 @@
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&clk_pclk3>;
clocks = <&rcc SYSCFG>;
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
@ -232,8 +195,9 @@
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&clk_pll4_p>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@ -246,8 +210,9 @@
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&clk_pll4_p>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@ -257,7 +222,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&clk_pclk4>, <&clk_lsi>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
@ -266,7 +231,8 @@
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>, <&clk_rtc_k>;
clocks = <&scmi_clk CK_SCMI_RTCAPB>,
<&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
status = "disabled";
};
@ -307,7 +273,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
@ -319,7 +285,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
@ -331,7 +297,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
@ -343,7 +309,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
@ -355,7 +321,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
@ -367,7 +333,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
@ -379,7 +345,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
@ -391,7 +357,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
@ -403,7 +369,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;

4
arch/arm/boot/dts/stm32mp133.dtsi
View File

@ -15,7 +15,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clk_hse>, <&clk_pll4_r>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@ -28,7 +28,7 @@
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clk_hse>, <&clk_pll4_r>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";

3
arch/arm/boot/dts/stm32mp13xc.dtsi
View File

@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_axi>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};

3
arch/arm/boot/dts/stm32mp13xf.dtsi
View File

@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_axi>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};