drm/amd/display: Add Freesync HDMI support to DM
[Why] Add necessary support for Freesync HDMI in Linux DM [How] - Support Freesync HDMI by calling DC interace - Report Freesync capability to vrr_range debugfs from DRM - Depends on coming DMCU/DMUB firmware to enable feature Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Stylon Wang
Alex Deucher
parent
00e9d4c0ab
commit
f9b4f20c47
@ -34,6 +34,7 @@
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#include "dc/inc/hw/dmcu.h"
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#include "dc/inc/hw/abm.h"
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#include "dc/dc_dmub_srv.h"
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#include "dc/dc_edid_parser.h"
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#include "amdgpu_dm_trace.h"
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#include "vid.h"
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@ -6908,6 +6909,12 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
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*/
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drm_mode_sort(&connector->probed_modes);
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amdgpu_dm_get_native_mode(connector);
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/* Freesync capabilities are reset by calling
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* drm_add_edid_modes() and need to be
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* restored here.
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*/
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amdgpu_dm_update_freesync_caps(connector, edid);
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} else {
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amdgpu_dm_connector->num_modes = 0;
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}
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@ -9627,11 +9634,84 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc,
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return capable;
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}
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static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
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uint8_t *edid_ext, int len,
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struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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int i;
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struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
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struct dc *dc = adev->dm.dc;
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/* send extension block to DMCU for parsing */
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for (i = 0; i < len; i += 8) {
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bool res;
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int offset;
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/* send 8 bytes a time */
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if (!dc_edid_parser_send_cea(dc, i, len, &edid_ext[i], 8))
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return false;
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if (i+8 == len) {
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/* EDID block sent completed, expect result */
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int version, min_rate, max_rate;
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res = dc_edid_parser_recv_amd_vsdb(dc, &version, &min_rate, &max_rate);
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if (res) {
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/* amd vsdb found */
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vsdb_info->freesync_supported = 1;
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vsdb_info->amd_vsdb_version = version;
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vsdb_info->min_refresh_rate_hz = min_rate;
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vsdb_info->max_refresh_rate_hz = max_rate;
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return true;
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}
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/* not amd vsdb */
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return false;
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}
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/* check for ack*/
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res = dc_edid_parser_recv_cea_ack(dc, &offset);
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if (!res)
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return false;
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}
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return false;
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}
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static bool parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
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struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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uint8_t *edid_ext = NULL;
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int i;
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bool valid_vsdb_found = false;
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/*----- drm_find_cea_extension() -----*/
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/* No EDID or EDID extensions */
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if (edid == NULL || edid->extensions == 0)
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return false;
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/* Find CEA extension */
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for (i = 0; i < edid->extensions; i++) {
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edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
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if (edid_ext[0] == CEA_EXT)
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break;
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}
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if (i == edid->extensions)
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return false;
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/*----- cea_db_offsets() -----*/
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if (edid_ext[0] != CEA_EXT)
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return false;
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valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
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return valid_vsdb_found;
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}
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void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
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struct edid *edid)
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{
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int i;
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bool edid_check_required;
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struct detailed_timing *timing;
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struct detailed_non_pixel *data;
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struct detailed_data_monitor_range *range;
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@ -9642,6 +9722,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
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struct drm_device *dev = connector->dev;
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struct amdgpu_device *adev = drm_to_adev(dev);
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bool freesync_capable = false;
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struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
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bool hdmi_valid_vsdb_found = false;
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if (!connector->state) {
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DRM_ERROR("%s - Connector has no state", __func__);
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@ -9660,60 +9742,75 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
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dm_con_state = to_dm_connector_state(connector->state);
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edid_check_required = false;
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if (!amdgpu_dm_connector->dc_sink) {
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DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
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goto update;
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}
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if (!adev->dm.freesync_module)
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goto update;
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/*
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* if edid non zero restrict freesync only for dp and edp
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*/
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if (edid) {
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if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
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|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
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if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
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|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
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bool edid_check_required = false;
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if (edid) {
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edid_check_required = is_dp_capable_without_timing_msa(
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adev->dm.dc,
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amdgpu_dm_connector);
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}
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}
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if (edid_check_required == true && (edid->version > 1 ||
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(edid->version == 1 && edid->revision > 1))) {
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for (i = 0; i < 4; i++) {
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timing = &edid->detailed_timings[i];
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data = &timing->data.other_data;
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range = &data->data.range;
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/*
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* Check if monitor has continuous frequency mode
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*/
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if (data->type != EDID_DETAIL_MONITOR_RANGE)
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continue;
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/*
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* Check for flag range limits only. If flag == 1 then
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* no additional timing information provided.
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* Default GTF, GTF Secondary curve and CVT are not
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* supported
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*/
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if (range->flags != 1)
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continue;
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if (edid_check_required == true && (edid->version > 1 ||
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(edid->version == 1 && edid->revision > 1))) {
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for (i = 0; i < 4; i++) {
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amdgpu_dm_connector->min_vfreq = range->min_vfreq;
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amdgpu_dm_connector->max_vfreq = range->max_vfreq;
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amdgpu_dm_connector->pixel_clock_mhz =
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range->pixel_clock_mhz * 10;
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timing = &edid->detailed_timings[i];
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data = &timing->data.other_data;
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range = &data->data.range;
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/*
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* Check if monitor has continuous frequency mode
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*/
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if (data->type != EDID_DETAIL_MONITOR_RANGE)
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continue;
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/*
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* Check for flag range limits only. If flag == 1 then
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* no additional timing information provided.
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* Default GTF, GTF Secondary curve and CVT are not
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* supported
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*/
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if (range->flags != 1)
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continue;
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connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
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connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
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amdgpu_dm_connector->min_vfreq = range->min_vfreq;
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amdgpu_dm_connector->max_vfreq = range->max_vfreq;
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amdgpu_dm_connector->pixel_clock_mhz =
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range->pixel_clock_mhz * 10;
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break;
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connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
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connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
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break;
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}
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if (amdgpu_dm_connector->max_vfreq -
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amdgpu_dm_connector->min_vfreq > 10) {
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freesync_capable = true;
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}
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}
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} else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
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hdmi_valid_vsdb_found = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
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if (hdmi_valid_vsdb_found && vsdb_info.freesync_supported) {
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timing = &edid->detailed_timings[i];
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data = &timing->data.other_data;
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if (amdgpu_dm_connector->max_vfreq -
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amdgpu_dm_connector->min_vfreq > 10) {
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amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
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amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
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if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
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freesync_capable = true;
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freesync_capable = true;
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connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
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connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
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}
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}
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@ -474,6 +474,14 @@ struct dm_connector_state {
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uint64_t pbn;
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};
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struct amdgpu_hdmi_vsdb_info {
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unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */
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bool freesync_supported; /* FreeSync Supported */
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unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */
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unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */
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};
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#define to_dm_connector_state(x)\
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container_of((x), struct dm_connector_state, base)
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