ASoC: cs42l73: Namespace defines for cs42l73 codec
Cleanup to namespace the defines for the cs42l73 driver Signed-off-by: Brian Austin <brian.austin@cirrus.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -1047,11 +1047,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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mmcc |= MS_MASTER;
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mmcc |= CS42L73_MS_MASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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mmcc &= ~MS_MASTER;
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mmcc &= ~CS42L73_MS_MASTER;
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break;
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default:
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@ -1063,11 +1063,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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switch (format) {
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case SND_SOC_DAIFMT_I2S:
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spc &= ~SPDIF_PCM;
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spc &= ~CS42L73_SPDIF_PCM;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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if (mmcc & MS_MASTER) {
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if (mmcc & CS42L73_MS_MASTER) {
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dev_err(codec->dev,
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"PCM format in slave mode only\n");
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return -EINVAL;
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@ -1077,25 +1077,25 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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"PCM format is not supported on ASP port\n");
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return -EINVAL;
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}
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spc |= SPDIF_PCM;
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spc |= CS42L73_SPDIF_PCM;
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break;
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default:
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return -EINVAL;
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}
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if (spc & SPDIF_PCM) {
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if (spc & CS42L73_SPDIF_PCM) {
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/* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
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spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER);
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spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
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switch (format) {
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case SND_SOC_DAIFMT_DSP_B:
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if (inv == SND_SOC_DAIFMT_IB_IF)
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spc |= PCM_MODE0;
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spc |= CS42L73_PCM_MODE0;
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if (inv == SND_SOC_DAIFMT_IB_NF)
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spc |= PCM_MODE1;
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spc |= CS42L73_PCM_MODE1;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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if (inv == SND_SOC_DAIFMT_IB_IF)
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spc |= PCM_MODE1;
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spc |= CS42L73_PCM_MODE1;
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break;
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default:
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return -EINVAL;
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@ -1155,7 +1155,7 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
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int mclk_coeff;
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int srate = params_rate(params);
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if (priv->config[id].mmcc & MS_MASTER) {
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if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
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/* CS42L73 Master */
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/* MCLK -> srate */
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mclk_coeff =
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@ -1174,13 +1174,13 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
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priv->config[id].spc &= 0xFC;
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/* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
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if (priv->mclk >= 6400000)
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priv->config[id].spc |= MCK_SCLK_64FS;
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priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
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else
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priv->config[id].spc |= MCK_SCLK_MCLK;
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priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
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} else {
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/* CS42L73 Slave */
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priv->config[id].spc &= 0xFC;
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priv->config[id].spc |= MCK_SCLK_64FS;
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priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
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}
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/* Update ASRCs */
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priv->config[id].srate = srate;
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@ -1200,8 +1200,8 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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switch (level) {
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case SND_SOC_BIAS_ON:
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snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0);
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snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 0);
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break;
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case SND_SOC_BIAS_PREPARE:
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@ -1212,11 +1212,11 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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regcache_cache_only(cs42l73->regmap, false);
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regcache_sync(cs42l73->regmap);
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}
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
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break;
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case SND_SOC_BIAS_OFF:
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
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if (cs42l73->shutdwn_delay > 0) {
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mdelay(cs42l73->shutdwn_delay);
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cs42l73->shutdwn_delay = 0;
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@ -1225,7 +1225,7 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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* down.
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*/
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}
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snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1);
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snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
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break;
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}
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codec->dapm.bias_level = level;
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@ -128,60 +128,60 @@
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/* Bitfield Definitions */
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/* CS42L73_PWRCTL1 */
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#define PDN_ADCB (1 << 7)
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#define PDN_DMICB (1 << 6)
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#define PDN_ADCA (1 << 5)
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#define PDN_DMICA (1 << 4)
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#define PDN_LDO (1 << 2)
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#define DISCHG_FILT (1 << 1)
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#define PDN (1 << 0)
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#define CS42L73_PDN_ADCB (1 << 7)
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#define CS42L73_PDN_DMICB (1 << 6)
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#define CS42L73_PDN_ADCA (1 << 5)
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#define CS42L73_PDN_DMICA (1 << 4)
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#define CS42L73_PDN_LDO (1 << 2)
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#define CS42L73_DISCHG_FILT (1 << 1)
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#define CS42L73_PDN (1 << 0)
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/* CS42L73_PWRCTL2 */
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#define PDN_MIC2_BIAS (1 << 7)
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#define PDN_MIC1_BIAS (1 << 6)
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#define PDN_VSP (1 << 4)
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#define PDN_ASP_SDOUT (1 << 3)
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#define PDN_ASP_SDIN (1 << 2)
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#define PDN_XSP_SDOUT (1 << 1)
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#define PDN_XSP_SDIN (1 << 0)
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#define CS42L73_PDN_MIC2_BIAS (1 << 7)
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#define CS42L73_PDN_MIC1_BIAS (1 << 6)
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#define CS42L73_PDN_VSP (1 << 4)
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#define CS42L73_PDN_ASP_SDOUT (1 << 3)
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#define CS42L73_PDN_ASP_SDIN (1 << 2)
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#define CS42L73_PDN_XSP_SDOUT (1 << 1)
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#define CS42L73_PDN_XSP_SDIN (1 << 0)
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/* CS42L73_PWRCTL3 */
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#define PDN_THMS (1 << 5)
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#define PDN_SPKLO (1 << 4)
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#define PDN_EAR (1 << 3)
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#define PDN_SPK (1 << 2)
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#define PDN_LO (1 << 1)
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#define PDN_HP (1 << 0)
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#define CS42L73_PDN_THMS (1 << 5)
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#define CS42L73_PDN_SPKLO (1 << 4)
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#define CS42L73_PDN_EAR (1 << 3)
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#define CS42L73_PDN_SPK (1 << 2)
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#define CS42L73_PDN_LO (1 << 1)
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#define CS42L73_PDN_HP (1 << 0)
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/* Thermal Overload Detect. Requires interrupt ... */
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#define THMOVLD_150C 0
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#define THMOVLD_132C 1
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#define THMOVLD_115C 2
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#define THMOVLD_098C 3
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#define CS42L73_THMOVLD_150C 0
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#define CS42L73_THMOVLD_132C 1
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#define CS42L73_THMOVLD_115C 2
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#define CS42L73_THMOVLD_098C 3
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#define CS42L73_CHARGEPUMP_MASK (0xF0)
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/* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */
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#define SP_3ST (1 << 7)
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#define SPDIF_I2S (0 << 6)
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#define SPDIF_PCM (1 << 6)
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#define PCM_MODE0 (0 << 4)
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#define PCM_MODE1 (1 << 4)
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#define PCM_MODE2 (2 << 4)
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#define PCM_MODE_MASK (3 << 4)
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#define PCM_BIT_ORDER (1 << 3)
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#define MCK_SCLK_64FS (0 << 0)
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#define MCK_SCLK_MCLK (2 << 0)
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#define MCK_SCLK_PREMCLK (3 << 0)
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#define CS42L73_SP_3ST (1 << 7)
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#define CS42L73_SPDIF_I2S (0 << 6)
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#define CS42L73_SPDIF_PCM (1 << 6)
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#define CS42L73_PCM_MODE0 (0 << 4)
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#define CS42L73_PCM_MODE1 (1 << 4)
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#define CS42L73_PCM_MODE2 (2 << 4)
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#define CS42L73_PCM_MODE_MASK (3 << 4)
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#define CS42L73_PCM_BIT_ORDER (1 << 3)
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#define CS42L73_MCK_SCLK_64FS (0 << 0)
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#define CS42L73_MCK_SCLK_MCLK (2 << 0)
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#define CS42L73_MCK_SCLK_PREMCLK (3 << 0)
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/* CS42L73_xSPMMCC */
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#define MS_MASTER (1 << 7)
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#define CS42L73_MS_MASTER (1 << 7)
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/* CS42L73_DMMCC */
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#define MCLKDIS (1 << 0)
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#define MCLKSEL_MCLK2 (1 << 4)
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#define MCLKSEL_MCLK1 (0 << 4)
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#define CS42L73_MCLKDIS (1 << 0)
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#define CS42L73_MCLKSEL_MCLK2 (1 << 4)
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#define CS42L73_MCLKSEL_MCLK1 (0 << 4)
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/* CS42L73 MCLK derived from MCLK1 or MCLK2 */
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#define CS42L73_CLKID_MCLK1 0
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@ -195,28 +195,26 @@
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#define CS42L73_VSP 2
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/* IS1, IM1 */
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#define MIC2_SDET (1 << 6)
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#define THMOVLD (1 << 4)
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#define DIGMIXOVFL (1 << 3)
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#define IPBOVFL (1 << 1)
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#define IPAOVFL (1 << 0)
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#define CS42L73_MIC2_SDET (1 << 6)
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#define CS42L73_THMOVLD (1 << 4)
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#define CS42L73_DIGMIXOVFL (1 << 3)
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#define CS42L73_IPBOVFL (1 << 1)
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#define CS42L73_IPAOVFL (1 << 0)
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/* Analog Softramp */
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#define ANLGOSFT (1 << 0)
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#define CS42L73_ANLGOSFT (1 << 0)
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/* HP A/B Analog Mute */
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#define HPA_MUTE (1 << 7)
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#define CS42L73_HPA_MUTE (1 << 7)
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/* LO A/B Analog Mute */
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#define LOA_MUTE (1 << 7)
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#define CS42L73_LOA_MUTE (1 << 7)
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/* Digital Mute */
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#define HLAD_MUTE (1 << 0)
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#define HLBD_MUTE (1 << 1)
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#define SPKD_MUTE (1 << 2)
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#define ESLD_MUTE (1 << 3)
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#define CS42L73_HLAD_MUTE (1 << 0)
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#define CS42L73_HLBD_MUTE (1 << 1)
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#define CS42L73_SPKD_MUTE (1 << 2)
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#define CS42L73_ESLD_MUTE (1 << 3)
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/* Misc defines for codec */
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#define CS42L73_RESET_GPIO 143
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#define CS42L73_DEVID 0x00042A73
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#define CS42L73_MCLKX_MIN 5644800
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#define CS42L73_MCLKX_MAX 38400000
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