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PCI/ERR: Use PCI_POSSIBLE_ERROR() to check config reads

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When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Link: https://lore.kernel.org/r/f4d18d470cb90f9cb52ea155b01528ba2e76e8d6.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Naveen Naidu 2021-11-18 19:33:26 +05:30 committed by Bjorn Helgaas
parent ba25d181ca
commit fa52b6447c
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/pci/pci.c
View File

@ -1115,7 +1115,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
return -EIO; return -EIO;
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
if (pmcsr == (u16) ~0) { if (PCI_POSSIBLE_ERROR(pmcsr)) {
pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
pci_power_name(dev->current_state), pci_power_name(dev->current_state),
pci_power_name(state)); pci_power_name(state));
@ -1271,16 +1271,16 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
* After reset, the device should not silently discard config * After reset, the device should not silently discard config
* requests, but it may still indicate that it needs more time by * requests, but it may still indicate that it needs more time by
* responding to them with CRS completions. The Root Port will * responding to them with CRS completions. The Root Port will
* generally synthesize ~0 data to complete the read (except when * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
* CRS SV is enabled and the read was for the Vendor ID; in that * the read (except when CRS SV is enabled and the read was for the
* case it synthesizes 0x0001 data). * Vendor ID; in that case it synthesizes 0x0001 data).
* *
* Wait for the device to return a non-CRS completion. Read the * Wait for the device to return a non-CRS completion. Read the
* Command register instead of Vendor ID so we don't have to * Command register instead of Vendor ID so we don't have to
* contend with the CRS SV value. * contend with the CRS SV value.
*/ */
pci_read_config_dword(dev, PCI_COMMAND, &id); pci_read_config_dword(dev, PCI_COMMAND, &id);
while (id == ~0) { while (PCI_POSSIBLE_ERROR(id)) {
if (delay > timeout) { if (delay > timeout) {
pci_warn(dev, "not ready %dms after %s; giving up\n", pci_warn(dev, "not ready %dms after %s; giving up\n",
delay - 1, reset_type); delay - 1, reset_type);

10
drivers/pci/probe.c
View File

@ -206,14 +206,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
* 1 must be clear. * 1 must be clear.
*/ */
if (sz == 0xffffffff) if (PCI_POSSIBLE_ERROR(sz))
sz = 0; sz = 0;
/* /*
* I don't know how l can have all bits set. Copied from old code. * I don't know how l can have all bits set. Copied from old code.
* Maybe it fixes a bug on some ancient platform. * Maybe it fixes a bug on some ancient platform.
*/ */
if (l == 0xffffffff) if (PCI_POSSIBLE_ERROR(l))
l = 0; l = 0;
if (type == pci_bar_unknown) { if (type == pci_bar_unknown) {
@ -1683,7 +1683,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
return PCI_CFG_SPACE_SIZE; return PCI_CFG_SPACE_SIZE;
if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
return PCI_CFG_SPACE_SIZE; return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_EXP_SIZE; return PCI_CFG_SPACE_EXP_SIZE;
@ -2371,8 +2371,8 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
return false; return false;
/* Some broken boards return 0 or ~0 if a slot is empty: */ /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
if (*l == 0xffffffff || *l == 0x00000000 || if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
*l == 0x0000ffff || *l == 0xffff0000) *l == 0x0000ffff || *l == 0xffff0000)
return false; return false;