EDAC/altera, firmware/intel: Add Stratix10 ECC DBE SMC call
Reserve ECC Double Bit Error SMC call to alert U-Boot that a DBE has occurred. Move the call from local EDAC header file to a common header. [ bp: Merge the two patches. ] Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Richard Gong <richard.gong@intel.com> Reviewed-by: Alan Tull <atull@kernel.org> # firmware Cc: Greg KH <greg@kroah.com> Cc: James Morse <james.morse@arm.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@kernel.org Link: https://lkml.kernel.org/r/1553870639-23895-1-git-send-email-thor.thayer@linux.intel.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Thor Thayer
Borislav Petkov
parent
788586efd1
commit
fad9fab975
@ -9,6 +9,7 @@
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#include <linux/ctype.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/edac.h>
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#include <linux/edac.h>
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#include <linux/firmware/intel/stratix10-smc.h>
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#include <linux/genalloc.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/chained_irq.h>
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@ -372,87 +372,4 @@ struct altr_arria10_edac {
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struct notifier_block panic_notifier;
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struct notifier_block panic_notifier;
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};
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};
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/*
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* Functions specified by ARM SMC Calling convention:
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*
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* FAST call executes atomic operations, returns when the requested operation
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* has completed.
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* STD call starts a operation which can be preempted by a non-secure
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* interrupt. The call can return before the requested operation has
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* completed.
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*
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* a0..a7 is used as register names in the descriptions below, on arm32
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* that translates to r0..r7 and on arm64 to w0..w7.
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*/
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#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
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ARM_SMCCC_OWNER_SIP, (func_num))
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#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
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ARM_SMCCC_OWNER_SIP, (func_num))
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#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
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#define INTEL_SIP_SMC_STATUS_OK 0x0
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#define INTEL_SIP_SMC_REG_ERROR 0x5
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/*
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* Request INTEL_SIP_SMC_REG_READ
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*
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* Read a protected register using SMCCC
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*
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* Call register usage:
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* a0: INTEL_SIP_SMC_REG_READ.
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* a1: register address.
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* a2-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
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* INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
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* a1: Value in the register
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* a2-3: not used.
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*/
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#define INTEL_SIP_SMC_FUNCID_REG_READ 7
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#define INTEL_SIP_SMC_REG_READ \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
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/*
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* Request INTEL_SIP_SMC_REG_WRITE
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*
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* Write a protected register using SMCCC
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*
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* Call register usage:
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* a0: INTEL_SIP_SMC_REG_WRITE.
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* a1: register address
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* a2: value to program into register.
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* a3-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
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* INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
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* a1-3: not used.
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*/
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#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
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#define INTEL_SIP_SMC_REG_WRITE \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
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/*
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* Request INTEL_SIP_SMC_ECC_DBE
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*
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* Sync call used by service driver at EL1 alert EL3 that a Double Bit
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* ECC error has occurred.
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*
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* Call register usage:
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* a0 INTEL_SIP_SMC_ECC_DBE
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* a1 SysManager Double Bit Error value
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* a2-7 not used
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*
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* Return status
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* a0 INTEL_SIP_SMC_STATUS_OK
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*/
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#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
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#define INTEL_SIP_SMC_ECC_DBE \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
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#endif /* #ifndef _ALTERA_EDAC_H */
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#endif /* #ifndef _ALTERA_EDAC_H */
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@ -309,4 +309,23 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
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#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
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#define INTEL_SIP_SMC_RSU_UPDATE \
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#define INTEL_SIP_SMC_RSU_UPDATE \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
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/*
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* Request INTEL_SIP_SMC_ECC_DBE
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*
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* Sync call used by service driver at EL1 to alert EL3 that a Double
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* Bit ECC error has occurred.
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*
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* Call register usage:
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* a0 INTEL_SIP_SMC_ECC_DBE
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* a1 SysManager Double Bit Error value
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* a2-7 not used
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*
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* Return status
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* a0 INTEL_SIP_SMC_STATUS_OK
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*/
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#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
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#define INTEL_SIP_SMC_ECC_DBE \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
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#endif
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#endif
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