iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: everest: Add phase corrections for eMMC

Browse Source 
The values were determined experimentally via boot tests, not by
measuring the bus behaviour with a scope. We plan to do scope
measurements to confirm or refine the values and will update the
devicetree if necessary once these have been obtained.

However, with the patch we can write and read data without issue, where
as booting the system without the patch failed at the point of mounting
the rootfs.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210628013605.1257346-1-andrew@aj.id.au
Fixes: 2fc88f92359d ("mmc: sdhci-of-aspeed: Expose clock phase controls")
Fixes: a5c5168478d7 ("ARM: dts: aspeed: Add Everest BMC machine")
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Andrew Jeffery 2021-06-28 11:06:05 +09:30 committed by Joel Stanley
parent 2d6608b57c
commit faffd1b2bd
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
View File

@ -2832,6 +2832,7 @@
&emmc {
status = "okay";
clk-phase-mmc-hs200 = <180>, <180>;
};
&fsim0 {