drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
Not sure where the single pipe only restriction came for fbc1. Nothing I can see that would prevent this. v2: Nuke no_fbc_on_multiple_pipes() too Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191127201222.16669-3-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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@ -17810,8 +17810,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
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}
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intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
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intel_fbc_init_pipe_state(dev_priv);
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}
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void intel_display_resume(struct drm_device *dev)
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@ -50,11 +50,6 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv)
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return HAS_FBC(dev_priv);
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}
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static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
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{
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return INTEL_GEN(dev_priv) <= 3;
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}
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/*
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* In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
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* frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
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@ -419,25 +414,6 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
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fbc->no_fbc_reason = reason;
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}
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static bool multiple_pipes_ok(struct intel_crtc *crtc,
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const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_fbc *fbc = &dev_priv->fbc;
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enum pipe pipe = crtc->pipe;
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/* Don't even bother tracking anything we don't need. */
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if (!no_fbc_on_multiple_pipes(dev_priv))
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return true;
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if (plane_state->uapi.visible)
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fbc->visible_pipes_mask |= (1 << pipe);
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else
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fbc->visible_pipes_mask &= ~(1 << pipe);
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return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
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}
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static int find_compression_threshold(struct drm_i915_private *dev_priv,
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struct drm_mm_node *node,
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int size,
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@ -867,18 +843,12 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
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mutex_lock(&fbc->lock);
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if (!multiple_pipes_ok(crtc, plane_state)) {
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reason = "more than one pipe active";
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goto deactivate;
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}
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if (!fbc->enabled || fbc->crtc != crtc)
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goto unlock;
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intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
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fbc->flip_pending = true;
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deactivate:
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intel_fbc_deactivate(dev_priv, reason);
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unlock:
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mutex_unlock(&fbc->lock);
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@ -1244,28 +1214,6 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
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schedule_work(&fbc->underrun_work);
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}
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/**
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* intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
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* @dev_priv: i915 device instance
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*
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* The FBC code needs to track CRTC visibility since the older platforms can't
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* have FBC enabled while multiple pipes are used. This function does the
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* initial setup at driver load to make sure FBC is matching the real hardware.
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*/
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void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
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{
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struct intel_crtc *crtc;
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/* Don't even bother tracking anything if we don't need. */
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if (!no_fbc_on_multiple_pipes(dev_priv))
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return;
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for_each_intel_crtc(&dev_priv->drm, crtc)
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if (intel_crtc_active(crtc) &&
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crtc->base.primary->state->visible)
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dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
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}
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/*
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* The DDX driver changes its behavior depending on the value it reads from
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* i915.enable_fbc, so sanitize it by translating the default value into either
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@ -24,7 +24,6 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
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const struct intel_plane_state *plane_state);
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void intel_fbc_post_update(struct intel_crtc *crtc);
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void intel_fbc_init(struct drm_i915_private *dev_priv);
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void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
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void intel_fbc_enable(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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@ -366,7 +366,6 @@ struct intel_fbc {
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unsigned threshold;
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unsigned int possible_framebuffer_bits;
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unsigned int busy_bits;
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unsigned int visible_pipes_mask;
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struct intel_crtc *crtc;
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struct drm_mm_node compressed_fb;
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